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mikhailramalhomikhailramalho
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Added testcase
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‎llvm/test/CodeGen/RISCV/half-convert-strict.ll

Lines changed: 360 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2165,3 +2165,363 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) strictfp {
21652165
store half %4, ptr %1, align 2
21662166
ret i32 %3
21672167
}
2168+
2169+
define dso_local void @int_uint_to_half(i32 noundef %p1, i32 noundef %p2) {
2170+
; CHECKIZFH-LABEL: int_uint_to_half:
2171+
; CHECKIZFH: # %bb.0: # %entry
2172+
; CHECKIZFH-NEXT: addi sp, sp, -16
2173+
; CHECKIZFH-NEXT: .cfi_def_cfa_offset 16
2174+
; CHECKIZFH-NEXT: sw a0, 12(sp)
2175+
; CHECKIZFH-NEXT: sw a1, 8(sp)
2176+
; CHECKIZFH-NEXT: fcvt.h.w fa5, a0
2177+
; CHECKIZFH-NEXT: fsh fa5, 6(sp)
2178+
; CHECKIZFH-NEXT: fcvt.h.wu fa5, a1
2179+
; CHECKIZFH-NEXT: fsh fa5, 4(sp)
2180+
; CHECKIZFH-NEXT: addi sp, sp, 16
2181+
; CHECKIZFH-NEXT: ret
2182+
;
2183+
; CHECKIZHINX-LABEL: int_uint_to_half:
2184+
; CHECKIZHINX: # %bb.0: # %entry
2185+
; CHECKIZHINX-NEXT: addi sp, sp, -16
2186+
; CHECKIZHINX-NEXT: .cfi_def_cfa_offset 16
2187+
; CHECKIZHINX-NEXT: sw a0, 12(sp)
2188+
; CHECKIZHINX-NEXT: sw a1, 8(sp)
2189+
; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
2190+
; CHECKIZHINX-NEXT: sh a0, 6(sp)
2191+
; CHECKIZHINX-NEXT: fcvt.h.wu a0, a1
2192+
; CHECKIZHINX-NEXT: sh a0, 4(sp)
2193+
; CHECKIZHINX-NEXT: addi sp, sp, 16
2194+
; CHECKIZHINX-NEXT: ret
2195+
;
2196+
; RV32IDZFH-LABEL: int_uint_to_half:
2197+
; RV32IDZFH: # %bb.0: # %entry
2198+
; RV32IDZFH-NEXT: addi sp, sp, -16
2199+
; RV32IDZFH-NEXT: .cfi_def_cfa_offset 16
2200+
; RV32IDZFH-NEXT: sw a0, 12(sp)
2201+
; RV32IDZFH-NEXT: sw a1, 8(sp)
2202+
; RV32IDZFH-NEXT: fcvt.h.w fa5, a0
2203+
; RV32IDZFH-NEXT: fsh fa5, 6(sp)
2204+
; RV32IDZFH-NEXT: fcvt.h.wu fa5, a1
2205+
; RV32IDZFH-NEXT: fsh fa5, 4(sp)
2206+
; RV32IDZFH-NEXT: addi sp, sp, 16
2207+
; RV32IDZFH-NEXT: ret
2208+
;
2209+
; RV64IDZFH-LABEL: int_uint_to_half:
2210+
; RV64IDZFH: # %bb.0: # %entry
2211+
; RV64IDZFH-NEXT: addi sp, sp, -16
2212+
; RV64IDZFH-NEXT: .cfi_def_cfa_offset 16
2213+
; RV64IDZFH-NEXT: sw a0, 12(sp)
2214+
; RV64IDZFH-NEXT: sw a1, 8(sp)
2215+
; RV64IDZFH-NEXT: fcvt.h.w fa5, a0
2216+
; RV64IDZFH-NEXT: fsh fa5, 6(sp)
2217+
; RV64IDZFH-NEXT: fcvt.h.wu fa5, a1
2218+
; RV64IDZFH-NEXT: fsh fa5, 4(sp)
2219+
; RV64IDZFH-NEXT: addi sp, sp, 16
2220+
; RV64IDZFH-NEXT: ret
2221+
;
2222+
; RV32IZDINXZHINX-LABEL: int_uint_to_half:
2223+
; RV32IZDINXZHINX: # %bb.0: # %entry
2224+
; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
2225+
; RV32IZDINXZHINX-NEXT: .cfi_def_cfa_offset 16
2226+
; RV32IZDINXZHINX-NEXT: sw a0, 12(sp)
2227+
; RV32IZDINXZHINX-NEXT: sw a1, 8(sp)
2228+
; RV32IZDINXZHINX-NEXT: fcvt.h.w a0, a0
2229+
; RV32IZDINXZHINX-NEXT: sh a0, 6(sp)
2230+
; RV32IZDINXZHINX-NEXT: fcvt.h.wu a0, a1
2231+
; RV32IZDINXZHINX-NEXT: sh a0, 4(sp)
2232+
; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
2233+
; RV32IZDINXZHINX-NEXT: ret
2234+
;
2235+
; RV64IZDINXZHINX-LABEL: int_uint_to_half:
2236+
; RV64IZDINXZHINX: # %bb.0: # %entry
2237+
; RV64IZDINXZHINX-NEXT: addi sp, sp, -16
2238+
; RV64IZDINXZHINX-NEXT: .cfi_def_cfa_offset 16
2239+
; RV64IZDINXZHINX-NEXT: sw a0, 12(sp)
2240+
; RV64IZDINXZHINX-NEXT: sw a1, 8(sp)
2241+
; RV64IZDINXZHINX-NEXT: fcvt.h.w a0, a0
2242+
; RV64IZDINXZHINX-NEXT: sh a0, 6(sp)
2243+
; RV64IZDINXZHINX-NEXT: fcvt.h.wu a0, a1
2244+
; RV64IZDINXZHINX-NEXT: sh a0, 4(sp)
2245+
; RV64IZDINXZHINX-NEXT: addi sp, sp, 16
2246+
; RV64IZDINXZHINX-NEXT: ret
2247+
;
2248+
; CHECK32-IZFHMIN-LABEL: int_uint_to_half:
2249+
; CHECK32-IZFHMIN: # %bb.0: # %entry
2250+
; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
2251+
; CHECK32-IZFHMIN-NEXT: .cfi_def_cfa_offset 16
2252+
; CHECK32-IZFHMIN-NEXT: sw a0, 12(sp)
2253+
; CHECK32-IZFHMIN-NEXT: sw a1, 8(sp)
2254+
; CHECK32-IZFHMIN-NEXT: fcvt.s.w fa5, a0
2255+
; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2256+
; CHECK32-IZFHMIN-NEXT: fsh fa5, 6(sp)
2257+
; CHECK32-IZFHMIN-NEXT: fcvt.s.wu fa5, a1
2258+
; CHECK32-IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2259+
; CHECK32-IZFHMIN-NEXT: fsh fa5, 4(sp)
2260+
; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
2261+
; CHECK32-IZFHMIN-NEXT: ret
2262+
;
2263+
; CHECK64-IZFHMIN-LABEL: int_uint_to_half:
2264+
; CHECK64-IZFHMIN: # %bb.0: # %entry
2265+
; CHECK64-IZFHMIN-NEXT: addi sp, sp, -16
2266+
; CHECK64-IZFHMIN-NEXT: .cfi_def_cfa_offset 16
2267+
; CHECK64-IZFHMIN-NEXT: slli a2, a1, 32
2268+
; CHECK64-IZFHMIN-NEXT: srli a2, a2, 32
2269+
; CHECK64-IZFHMIN-NEXT: sext.w a3, a0
2270+
; CHECK64-IZFHMIN-NEXT: sw a0, 12(sp)
2271+
; CHECK64-IZFHMIN-NEXT: sw a1, 8(sp)
2272+
; CHECK64-IZFHMIN-NEXT: fcvt.s.l fa5, a3
2273+
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2274+
; CHECK64-IZFHMIN-NEXT: fsh fa5, 6(sp)
2275+
; CHECK64-IZFHMIN-NEXT: fcvt.s.lu fa5, a2
2276+
; CHECK64-IZFHMIN-NEXT: fcvt.h.s fa5, fa5
2277+
; CHECK64-IZFHMIN-NEXT: fsh fa5, 4(sp)
2278+
; CHECK64-IZFHMIN-NEXT: addi sp, sp, 16
2279+
; CHECK64-IZFHMIN-NEXT: ret
2280+
;
2281+
; CHECK32-IZHINXMIN-LABEL: int_uint_to_half:
2282+
; CHECK32-IZHINXMIN: # %bb.0: # %entry
2283+
; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
2284+
; CHECK32-IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2285+
; CHECK32-IZHINXMIN-NEXT: sw a0, 12(sp)
2286+
; CHECK32-IZHINXMIN-NEXT: sw a1, 8(sp)
2287+
; CHECK32-IZHINXMIN-NEXT: fcvt.s.w a0, a0
2288+
; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
2289+
; CHECK32-IZHINXMIN-NEXT: sh a0, 6(sp)
2290+
; CHECK32-IZHINXMIN-NEXT: fcvt.s.wu a0, a1
2291+
; CHECK32-IZHINXMIN-NEXT: fcvt.h.s a0, a0
2292+
; CHECK32-IZHINXMIN-NEXT: sh a0, 4(sp)
2293+
; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
2294+
; CHECK32-IZHINXMIN-NEXT: ret
2295+
;
2296+
; CHECK64-IZHINXMIN-LABEL: int_uint_to_half:
2297+
; CHECK64-IZHINXMIN: # %bb.0: # %entry
2298+
; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16
2299+
; CHECK64-IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2300+
; CHECK64-IZHINXMIN-NEXT: slli a2, a1, 32
2301+
; CHECK64-IZHINXMIN-NEXT: srli a2, a2, 32
2302+
; CHECK64-IZHINXMIN-NEXT: sext.w a3, a0
2303+
; CHECK64-IZHINXMIN-NEXT: sw a0, 12(sp)
2304+
; CHECK64-IZHINXMIN-NEXT: sw a1, 8(sp)
2305+
; CHECK64-IZHINXMIN-NEXT: fcvt.s.l a0, a3
2306+
; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
2307+
; CHECK64-IZHINXMIN-NEXT: sh a0, 6(sp)
2308+
; CHECK64-IZHINXMIN-NEXT: fcvt.s.lu a0, a2
2309+
; CHECK64-IZHINXMIN-NEXT: fcvt.h.s a0, a0
2310+
; CHECK64-IZHINXMIN-NEXT: sh a0, 4(sp)
2311+
; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16
2312+
; CHECK64-IZHINXMIN-NEXT: ret
2313+
;
2314+
; CHECK32-IZDINXZHINXMIN-LABEL: int_uint_to_half:
2315+
; CHECK32-IZDINXZHINXMIN: # %bb.0: # %entry
2316+
; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
2317+
; CHECK32-IZDINXZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2318+
; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 12(sp)
2319+
; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 8(sp)
2320+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.w a0, a0
2321+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
2322+
; CHECK32-IZDINXZHINXMIN-NEXT: sh a0, 6(sp)
2323+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.wu a0, a1
2324+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
2325+
; CHECK32-IZDINXZHINXMIN-NEXT: sh a0, 4(sp)
2326+
; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
2327+
; CHECK32-IZDINXZHINXMIN-NEXT: ret
2328+
;
2329+
; CHECK64-IZDINXZHINXMIN-LABEL: int_uint_to_half:
2330+
; CHECK64-IZDINXZHINXMIN: # %bb.0: # %entry
2331+
; CHECK64-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
2332+
; CHECK64-IZDINXZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2333+
; CHECK64-IZDINXZHINXMIN-NEXT: slli a2, a1, 32
2334+
; CHECK64-IZDINXZHINXMIN-NEXT: srli a2, a2, 32
2335+
; CHECK64-IZDINXZHINXMIN-NEXT: sext.w a3, a0
2336+
; CHECK64-IZDINXZHINXMIN-NEXT: sw a0, 12(sp)
2337+
; CHECK64-IZDINXZHINXMIN-NEXT: sw a1, 8(sp)
2338+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.l a0, a3
2339+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
2340+
; CHECK64-IZDINXZHINXMIN-NEXT: sh a0, 6(sp)
2341+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.lu a0, a2
2342+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.h.s a0, a0
2343+
; CHECK64-IZDINXZHINXMIN-NEXT: sh a0, 4(sp)
2344+
; CHECK64-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
2345+
; CHECK64-IZDINXZHINXMIN-NEXT: ret
2346+
entry:
2347+
%p1.addr = alloca i32, align 4
2348+
%p2.addr = alloca i32, align 4
2349+
%f1 = alloca half, align 2
2350+
%f2 = alloca half, align 2
2351+
store i32 %p1, ptr %p1.addr, align 4
2352+
store i32 %p2, ptr %p2.addr, align 4
2353+
%0 = load i32, ptr %p1.addr, align 4
2354+
%conv = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %0, metadata !"round.dynamic", metadata !"fpexcept.ignore") #2
2355+
store half %conv, ptr %f1, align 2
2356+
%1 = load i32, ptr %p2.addr, align 4
2357+
%conv1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %1, metadata !"round.dynamic", metadata !"fpexcept.ignore") #2
2358+
store half %conv1, ptr %f2, align 2
2359+
ret void
2360+
}
2361+
2362+
define dso_local void @half_to_int_uint(half noundef %p1) {
2363+
; CHECKIZFH-LABEL: half_to_int_uint:
2364+
; CHECKIZFH: # %bb.0: # %entry
2365+
; CHECKIZFH-NEXT: addi sp, sp, -16
2366+
; CHECKIZFH-NEXT: .cfi_def_cfa_offset 16
2367+
; CHECKIZFH-NEXT: fsh fa0, 14(sp)
2368+
; CHECKIZFH-NEXT: fcvt.w.h a0, fa0, rtz
2369+
; CHECKIZFH-NEXT: sw a0, 8(sp)
2370+
; CHECKIZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2371+
; CHECKIZFH-NEXT: sw a0, 4(sp)
2372+
; CHECKIZFH-NEXT: addi sp, sp, 16
2373+
; CHECKIZFH-NEXT: ret
2374+
;
2375+
; CHECKIZHINX-LABEL: half_to_int_uint:
2376+
; CHECKIZHINX: # %bb.0: # %entry
2377+
; CHECKIZHINX-NEXT: addi sp, sp, -16
2378+
; CHECKIZHINX-NEXT: .cfi_def_cfa_offset 16
2379+
; CHECKIZHINX-NEXT: sh a0, 14(sp)
2380+
; CHECKIZHINX-NEXT: fcvt.w.h a1, a0, rtz
2381+
; CHECKIZHINX-NEXT: sw a1, 8(sp)
2382+
; CHECKIZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2383+
; CHECKIZHINX-NEXT: sw a0, 4(sp)
2384+
; CHECKIZHINX-NEXT: addi sp, sp, 16
2385+
; CHECKIZHINX-NEXT: ret
2386+
;
2387+
; RV32IDZFH-LABEL: half_to_int_uint:
2388+
; RV32IDZFH: # %bb.0: # %entry
2389+
; RV32IDZFH-NEXT: addi sp, sp, -16
2390+
; RV32IDZFH-NEXT: .cfi_def_cfa_offset 16
2391+
; RV32IDZFH-NEXT: fsh fa0, 14(sp)
2392+
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
2393+
; RV32IDZFH-NEXT: sw a0, 8(sp)
2394+
; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2395+
; RV32IDZFH-NEXT: sw a0, 4(sp)
2396+
; RV32IDZFH-NEXT: addi sp, sp, 16
2397+
; RV32IDZFH-NEXT: ret
2398+
;
2399+
; RV64IDZFH-LABEL: half_to_int_uint:
2400+
; RV64IDZFH: # %bb.0: # %entry
2401+
; RV64IDZFH-NEXT: addi sp, sp, -16
2402+
; RV64IDZFH-NEXT: .cfi_def_cfa_offset 16
2403+
; RV64IDZFH-NEXT: fsh fa0, 14(sp)
2404+
; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
2405+
; RV64IDZFH-NEXT: sw a0, 8(sp)
2406+
; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
2407+
; RV64IDZFH-NEXT: sw a0, 4(sp)
2408+
; RV64IDZFH-NEXT: addi sp, sp, 16
2409+
; RV64IDZFH-NEXT: ret
2410+
;
2411+
; RV32IZDINXZHINX-LABEL: half_to_int_uint:
2412+
; RV32IZDINXZHINX: # %bb.0: # %entry
2413+
; RV32IZDINXZHINX-NEXT: addi sp, sp, -16
2414+
; RV32IZDINXZHINX-NEXT: .cfi_def_cfa_offset 16
2415+
; RV32IZDINXZHINX-NEXT: sh a0, 14(sp)
2416+
; RV32IZDINXZHINX-NEXT: fcvt.w.h a1, a0, rtz
2417+
; RV32IZDINXZHINX-NEXT: sw a1, 8(sp)
2418+
; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2419+
; RV32IZDINXZHINX-NEXT: sw a0, 4(sp)
2420+
; RV32IZDINXZHINX-NEXT: addi sp, sp, 16
2421+
; RV32IZDINXZHINX-NEXT: ret
2422+
;
2423+
; RV64IZDINXZHINX-LABEL: half_to_int_uint:
2424+
; RV64IZDINXZHINX: # %bb.0: # %entry
2425+
; RV64IZDINXZHINX-NEXT: addi sp, sp, -16
2426+
; RV64IZDINXZHINX-NEXT: .cfi_def_cfa_offset 16
2427+
; RV64IZDINXZHINX-NEXT: sh a0, 14(sp)
2428+
; RV64IZDINXZHINX-NEXT: fcvt.w.h a1, a0, rtz
2429+
; RV64IZDINXZHINX-NEXT: sw a1, 8(sp)
2430+
; RV64IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
2431+
; RV64IZDINXZHINX-NEXT: sw a0, 4(sp)
2432+
; RV64IZDINXZHINX-NEXT: addi sp, sp, 16
2433+
; RV64IZDINXZHINX-NEXT: ret
2434+
;
2435+
; CHECK32-IZFHMIN-LABEL: half_to_int_uint:
2436+
; CHECK32-IZFHMIN: # %bb.0: # %entry
2437+
; CHECK32-IZFHMIN-NEXT: addi sp, sp, -16
2438+
; CHECK32-IZFHMIN-NEXT: .cfi_def_cfa_offset 16
2439+
; CHECK32-IZFHMIN-NEXT: fsh fa0, 14(sp)
2440+
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2441+
; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2442+
; CHECK32-IZFHMIN-NEXT: sw a0, 8(sp)
2443+
; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
2444+
; CHECK32-IZFHMIN-NEXT: sw a0, 4(sp)
2445+
; CHECK32-IZFHMIN-NEXT: addi sp, sp, 16
2446+
; CHECK32-IZFHMIN-NEXT: ret
2447+
;
2448+
; CHECK64-IZFHMIN-LABEL: half_to_int_uint:
2449+
; CHECK64-IZFHMIN: # %bb.0: # %entry
2450+
; CHECK64-IZFHMIN-NEXT: addi sp, sp, -16
2451+
; CHECK64-IZFHMIN-NEXT: .cfi_def_cfa_offset 16
2452+
; CHECK64-IZFHMIN-NEXT: fsh fa0, 14(sp)
2453+
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2454+
; CHECK64-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
2455+
; CHECK64-IZFHMIN-NEXT: sw a0, 8(sp)
2456+
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
2457+
; CHECK64-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
2458+
; CHECK64-IZFHMIN-NEXT: sw a0, 4(sp)
2459+
; CHECK64-IZFHMIN-NEXT: addi sp, sp, 16
2460+
; CHECK64-IZFHMIN-NEXT: ret
2461+
;
2462+
; CHECK32-IZHINXMIN-LABEL: half_to_int_uint:
2463+
; CHECK32-IZHINXMIN: # %bb.0: # %entry
2464+
; CHECK32-IZHINXMIN-NEXT: addi sp, sp, -16
2465+
; CHECK32-IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2466+
; CHECK32-IZHINXMIN-NEXT: sh a0, 14(sp)
2467+
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
2468+
; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2469+
; CHECK32-IZHINXMIN-NEXT: sw a1, 8(sp)
2470+
; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
2471+
; CHECK32-IZHINXMIN-NEXT: sw a0, 4(sp)
2472+
; CHECK32-IZHINXMIN-NEXT: addi sp, sp, 16
2473+
; CHECK32-IZHINXMIN-NEXT: ret
2474+
;
2475+
; CHECK64-IZHINXMIN-LABEL: half_to_int_uint:
2476+
; CHECK64-IZHINXMIN: # %bb.0: # %entry
2477+
; CHECK64-IZHINXMIN-NEXT: addi sp, sp, -16
2478+
; CHECK64-IZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2479+
; CHECK64-IZHINXMIN-NEXT: sh a0, 14(sp)
2480+
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a1, a0
2481+
; CHECK64-IZHINXMIN-NEXT: fcvt.w.s a1, a1, rtz
2482+
; CHECK64-IZHINXMIN-NEXT: sw a1, 8(sp)
2483+
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
2484+
; CHECK64-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
2485+
; CHECK64-IZHINXMIN-NEXT: sw a0, 4(sp)
2486+
; CHECK64-IZHINXMIN-NEXT: addi sp, sp, 16
2487+
; CHECK64-IZHINXMIN-NEXT: ret
2488+
;
2489+
; CHECK32-IZDINXZHINXMIN-LABEL: half_to_int_uint:
2490+
; CHECK32-IZDINXZHINXMIN: # %bb.0: # %entry
2491+
; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
2492+
; CHECK32-IZDINXZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2493+
; CHECK32-IZDINXZHINXMIN-NEXT: sh a0, 14(sp)
2494+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
2495+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a1, a0, rtz
2496+
; CHECK32-IZDINXZHINXMIN-NEXT: sw a1, 8(sp)
2497+
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
2498+
; CHECK32-IZDINXZHINXMIN-NEXT: sw a0, 4(sp)
2499+
; CHECK32-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
2500+
; CHECK32-IZDINXZHINXMIN-NEXT: ret
2501+
;
2502+
; CHECK64-IZDINXZHINXMIN-LABEL: half_to_int_uint:
2503+
; CHECK64-IZDINXZHINXMIN: # %bb.0: # %entry
2504+
; CHECK64-IZDINXZHINXMIN-NEXT: addi sp, sp, -16
2505+
; CHECK64-IZDINXZHINXMIN-NEXT: .cfi_def_cfa_offset 16
2506+
; CHECK64-IZDINXZHINXMIN-NEXT: sh a0, 14(sp)
2507+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a1, a0
2508+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.w.s a1, a1, rtz
2509+
; CHECK64-IZDINXZHINXMIN-NEXT: sw a1, 8(sp)
2510+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
2511+
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
2512+
; CHECK64-IZDINXZHINXMIN-NEXT: sw a0, 4(sp)
2513+
; CHECK64-IZDINXZHINXMIN-NEXT: addi sp, sp, 16
2514+
; CHECK64-IZDINXZHINXMIN-NEXT: ret
2515+
entry:
2516+
%p1.addr = alloca half, align 2
2517+
%i1 = alloca i32, align 4
2518+
%i2 = alloca i32, align 4
2519+
store half %p1, ptr %p1.addr, align 2
2520+
%0 = load half, ptr %p1.addr, align 2
2521+
%conv = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %0, metadata !"fpexcept.ignore") #2
2522+
store i32 %conv, ptr %i1, align 4
2523+
%1 = load half, ptr %p1.addr, align 2
2524+
%conv1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %1, metadata !"fpexcept.ignore") #2
2525+
store i32 %conv1, ptr %i2, align 4
2526+
ret void
2527+
}

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