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Rebase IP
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‎llvm/lib/CodeGen/PeepholeOptimizer.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1868,7 +1868,6 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
18681868
// If we run into an instruction we can't fold across, discard
18691869
// the load candidates. Note: We might be able to fold *into* this
18701870
// instruction, so this needs to be after the folding logic.
1871-
// TODO: Try AA for a store?
18721871
if (MI->isLoadFoldBarrier()) {
18731872
LLVM_DEBUG(dbgs() << "Encountered load fold barrier on " << *MI);
18741873
FoldAsLoadDefCandidates.clear();

‎llvm/lib/Target/SystemZ/CMakeLists.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ add_llvm_target(SystemZCodeGen
2020
SystemZConstantPoolValue.cpp
2121
SystemZCopyPhysRegs.cpp
2222
SystemZElimCompare.cpp
23-
SystemZFinalizeRegMem.cpp
23+
SystemZFinalizeReassociation.cpp
2424
SystemZFrameLowering.cpp
2525
SystemZHazardRecognizer.cpp
2626
SystemZISelDAGToDAG.cpp

‎llvm/lib/Target/SystemZ/SystemZ.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -195,14 +195,14 @@ FunctionPass *createSystemZShortenInstPass(SystemZTargetMachine &TM);
195195
FunctionPass *createSystemZLongBranchPass(SystemZTargetMachine &TM);
196196
FunctionPass *createSystemZLDCleanupPass(SystemZTargetMachine &TM);
197197
FunctionPass *createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM);
198-
FunctionPass *createSystemZFinalizeRegMemPass(SystemZTargetMachine &TM);
198+
FunctionPass *createSystemZFinalizeReassociationPass(SystemZTargetMachine &TM);
199199
FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM);
200200
FunctionPass *createSystemZTDCPass();
201201

202202
void initializeSystemZCopyPhysRegsPass(PassRegistry &);
203203
void initializeSystemZDAGToDAGISelPass(PassRegistry &);
204204
void initializeSystemZElimComparePass(PassRegistry &);
205-
void initializeSystemZFinalizeRegMemPass(PassRegistry &);
205+
void initializeSystemZFinalizeReassociationPass(PassRegistry &);
206206
void initializeSystemZLDCleanupPass(PassRegistry &);
207207
void initializeSystemZLongBranchPass(PassRegistry &);
208208
void initializeSystemZPostRewritePass(PassRegistry &);

‎llvm/lib/Target/SystemZ/SystemZFinalizeRegMem.cpp renamed to ‎llvm/lib/Target/SystemZ/SystemZFinalizeReassociation.cpp

Lines changed: 28 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,37 +1,41 @@
1-
//===------- SystemZFinalizeRegMem.cpp - Finalize FP reg/mem folding ------===//
1+
//===---- SystemZFinalizeReassociation.cpp - Finalize FP reassociation ----===//
22
//
33
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
44
// See https://llvm.org/LICENSE.txt for license information.
55
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
66
//
77
//===----------------------------------------------------------------------===//
88
//
9-
// This pass converts any remaining reg/reg pseudos into the real target
10-
// instruction in cases where the peephole optimizer did not fold a load into
11-
// a reg/mem instruction.
9+
// This pass is the last step of the process of enabling reassociation with
10+
// the MachineCombiner. These are the steps involved:
11+
//
12+
// 1. Instruction selection: Disable reg/mem folding for any operations that
13+
// are reassociable since MachineCombiner will not succeed otherwise.
14+
// Select a reg/reg pseudo that pretends to clobber CC since the reg/mem
15+
// opcode clobbers it.
16+
//
17+
// 2. MachineCombiner: Performs reassociation with the reg/reg instructions.
18+
//
19+
// 3. PeepholeOptimizer: Fold loads into reg/mem instructions.
20+
//
21+
// 4. This pass: Convert any remaining reg/reg pseudos.
1222
//
1323
//===----------------------------------------------------------------------===//
1424

15-
#include "SystemZMachineFunctionInfo.h"
1625
#include "SystemZTargetMachine.h"
17-
#include "llvm/CodeGen/MachineDominators.h"
1826
#include "llvm/CodeGen/MachineFunctionPass.h"
19-
#include "llvm/CodeGen/MachineInstrBuilder.h"
20-
#include "llvm/CodeGen/MachineRegisterInfo.h"
2127
#include "llvm/CodeGen/TargetInstrInfo.h"
22-
#include "llvm/CodeGen/TargetRegisterInfo.h"
23-
#include "llvm/Target/TargetMachine.h"
2428

2529
using namespace llvm;
2630

2731
namespace {
2832

29-
class SystemZFinalizeRegMem : public MachineFunctionPass {
33+
class SystemZFinalizeReassociation : public MachineFunctionPass {
3034
public:
3135
static char ID;
32-
SystemZFinalizeRegMem()
33-
: MachineFunctionPass(ID), TII(nullptr), MRI(nullptr) {
34-
initializeSystemZFinalizeRegMemPass(*PassRegistry::getPassRegistry());
36+
SystemZFinalizeReassociation()
37+
: MachineFunctionPass(ID), TII(nullptr) {
38+
initializeSystemZFinalizeReassociationPass(*PassRegistry::getPassRegistry());
3539
}
3640

3741
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -42,27 +46,26 @@ class SystemZFinalizeRegMem : public MachineFunctionPass {
4246
bool visitMBB(MachineBasicBlock &MBB);
4347

4448
const SystemZInstrInfo *TII;
45-
MachineRegisterInfo *MRI;
4649
};
4750

48-
char SystemZFinalizeRegMem::ID = 0;
51+
char SystemZFinalizeReassociation::ID = 0;
4952

5053
} // end anonymous namespace
5154

52-
INITIALIZE_PASS(SystemZFinalizeRegMem, "systemz-finalize-regmem",
53-
"SystemZ Finalize RegMem", false, false)
55+
INITIALIZE_PASS(SystemZFinalizeReassociation, "systemz-finalize-reassoc",
56+
"SystemZ Finalize Reassociation", false, false)
5457

5558
FunctionPass *llvm::
56-
createSystemZFinalizeRegMemPass(SystemZTargetMachine &TM) {
57-
return new SystemZFinalizeRegMem();
59+
createSystemZFinalizeReassociationPass(SystemZTargetMachine &TM) {
60+
return new SystemZFinalizeReassociation();
5861
}
5962

60-
void SystemZFinalizeRegMem::getAnalysisUsage(AnalysisUsage &AU) const {
63+
void SystemZFinalizeReassociation::getAnalysisUsage(AnalysisUsage &AU) const {
6164
AU.setPreservesCFG();
6265
MachineFunctionPass::getAnalysisUsage(AU);
6366
}
6467

65-
bool SystemZFinalizeRegMem::visitMBB(MachineBasicBlock &MBB) {
68+
bool SystemZFinalizeReassociation::visitMBB(MachineBasicBlock &MBB) {
6669
bool Changed = false;
6770
for (MachineInstr &MI : MBB) {
6871
unsigned PseudoOpcode = MI.getOpcode();
@@ -71,8 +74,8 @@ bool SystemZFinalizeRegMem::visitMBB(MachineBasicBlock &MBB) {
7174
: PseudoOpcode == SystemZ::WFASB_CCPseudo ? SystemZ::WFASB
7275
: PseudoOpcode == SystemZ::WFSDB_CCPseudo ? SystemZ::WFSDB
7376
: PseudoOpcode == SystemZ::WFSSB_CCPseudo ? SystemZ::WFSSB
74-
: PseudoOpcode == SystemZ::WFMADB_CCPseudo ? SystemZ::WFMADB
75-
: PseudoOpcode == SystemZ::WFMASB_CCPseudo ? SystemZ::WFMASB
77+
: PseudoOpcode == SystemZ::WFMADB_CCPseudo ? SystemZ::WFMADB
78+
: PseudoOpcode == SystemZ::WFMASB_CCPseudo ? SystemZ::WFMASB
7679
: 0;
7780
if (TargetOpcode) {
7881
MI.setDesc(TII->get(TargetOpcode));
@@ -84,9 +87,8 @@ bool SystemZFinalizeRegMem::visitMBB(MachineBasicBlock &MBB) {
8487
return Changed;
8588
}
8689

87-
bool SystemZFinalizeRegMem::runOnMachineFunction(MachineFunction &F) {
90+
bool SystemZFinalizeReassociation::runOnMachineFunction(MachineFunction &F) {
8891
TII = F.getSubtarget<SystemZSubtarget>().getInstrInfo();
89-
MRI = &F.getRegInfo();
9092

9193
bool Modified = false;
9294
for (auto &MBB : F)

‎llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -350,6 +350,11 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
350350
// Try to expand a boolean SELECT_CCMASK using an IPM sequence.
351351
SDValue expandSelectBoolean(SDNode *Node);
352352

353+
// Return true if the flags of N and the subtarget allows for
354+
// reassociation, in which case a reg/reg opcode is needed as input to the
355+
// MachineCombiner.
356+
bool shouldSelectForReassoc(SDNode *N) const;
357+
353358
public:
354359
static char ID;
355360

@@ -2044,6 +2049,16 @@ SDValue SystemZDAGToDAGISel::expandSelectBoolean(SDNode *Node) {
20442049
return Result;
20452050
}
20462051

2052+
bool SystemZDAGToDAGISel::shouldSelectForReassoc(SDNode *N) const {
2053+
EVT VT = N->getValueType(0);
2054+
assert(VT.isFloatingPoint() && "Expected FP SDNode");
2055+
return N->getFlags().hasAllowReassociation() &&
2056+
N->getFlags().hasNoSignedZeros() &&
2057+
Subtarget->hasVector() &&
2058+
(VT != MVT::f32 || Subtarget->hasVectorEnhancements1()) &&
2059+
!N->isStrictFPOpcode();
2060+
}
2061+
20472062
void SystemZDAGToDAGISel::PreprocessISelDAG() {
20482063
// If we have conditional immediate loads, we always prefer
20492064
// using those over an IPM sequence.

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -686,10 +686,6 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
686686
setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
687687
}
688688

689-
// Don't select reg/mem LDEB if WLDEB is available.
690-
if (Subtarget.hasVector())
691-
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
692-
693689
// Floating-point truncation and stores need to be done separately.
694690
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
695691
setTruncStoreAction(MVT::f128, MVT::f32, Expand);

‎llvm/lib/Target/SystemZ/SystemZInstrFP.td

Lines changed: 18 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,6 @@ let Predicates = [FeatureNoVectorEnhancements1] in {
201201
// Extend memory floating-point values to wider representations.
202202
let Uses = [FPC], mayRaiseFPException = 1 in {
203203
def LDEB : UnaryRXE<"ldeb", 0xED04, z_any_extloadf32, FP64, 4>;
204-
def LDEB : UnaryRXE<"ldeb", 0xED04, z_fpr_any_extloadf32, FP64, 4>;
205204
def LXEB : UnaryRXE<"lxeb", 0xED06, null_frag, FP128, 4>;
206205
def LXDB : UnaryRXE<"lxdb", 0xED05, null_frag, FP128, 8>;
207206
}
@@ -363,8 +362,8 @@ let Uses = [FPC], mayRaiseFPException = 1 in {
363362
def SQDBR : UnaryRRE<"sqdbr", 0xB315, any_fsqrt, FP64, FP64>;
364363
def SQXBR : UnaryRRE<"sqxbr", 0xB316, any_fsqrt, FP128, FP128>;
365364

366-
def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<any_fsqrt, z_fprload>, FP32, 4>;
367-
def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<any_fsqrt, z_fprload>, FP64, 8>;
365+
def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<any_fsqrt>, FP32, 4>;
366+
def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<any_fsqrt>, FP64, 8>;
368367
}
369368

370369
// Round to an integer, with the second operand (modifier M3) specifying
@@ -431,10 +430,10 @@ let Uses = [FPC], mayRaiseFPException = 1,
431430
def ADBR : BinaryRRE<"adbr", 0xB31A, any_fadd, FP64, FP64>;
432431
def AXBR : BinaryRRE<"axbr", 0xB34A, any_fadd, FP128, FP128>;
433432
}
434-
defm AEB : BinaryRXEAndPseudo<"aeb", 0xED0A, any_fadd, FP32, z_load, 4>;
435-
defm ADB : BinaryRXEAndPseudo<"adb", 0xED1A, any_fadd, FP64, z_load, 8>;
436-
defm AEB : BinaryRXEAndPseudo<"aeb", 0xED0A, any_fadd, FP32, z_fprload, 4>;
437-
defm ADB : BinaryRXEAndPseudo<"adb", 0xED1A, any_fadd, FP64, z_fprload, 8>;
433+
defm AEB : BinaryRXEAndPseudo<"aeb", 0xED0A, z_any_fadd_noreassoc, FP32,
434+
z_load, 4>;
435+
defm ADB : BinaryRXEAndPseudo<"adb", 0xED1A, z_any_fadd_noreassoc, FP64,
436+
z_load, 8>;
438437
}
439438

440439
// Subtraction.
@@ -444,10 +443,10 @@ let Uses = [FPC], mayRaiseFPException = 1,
444443
def SDBR : BinaryRRE<"sdbr", 0xB31B, any_fsub, FP64, FP64>;
445444
def SXBR : BinaryRRE<"sxbr", 0xB34B, any_fsub, FP128, FP128>;
446445

447-
defm SEB : BinaryRXEAndPseudo<"seb", 0xED0B, any_fsub, FP32, z_load, 4>;
448-
defm SDB : BinaryRXEAndPseudo<"sdb", 0xED1B, any_fsub, FP64, z_load, 8>;
449-
defm SEB : BinaryRXEAndPseudo<"seb", 0xED0B, any_fsub, FP32, z_fprload, 4>;
450-
defm SDB : BinaryRXEAndPseudo<"sdb", 0xED1B, any_fsub, FP64, z_fprload, 8>;
446+
defm SEB : BinaryRXEAndPseudo<"seb", 0xED0B, z_any_fsub_noreassoc, FP32,
447+
z_load, 4>;
448+
defm SDB : BinaryRXEAndPseudo<"sdb", 0xED1B, z_any_fsub_noreassoc, FP64,
449+
z_load, 8>;
451450
}
452451

453452
// Multiplication.
@@ -457,10 +456,10 @@ let Uses = [FPC], mayRaiseFPException = 1 in {
457456
def MDBR : BinaryRRE<"mdbr", 0xB31C, any_fmul, FP64, FP64>;
458457
def MXBR : BinaryRRE<"mxbr", 0xB34C, any_fmul, FP128, FP128>;
459458
}
460-
defm MEEB : BinaryRXEAndPseudo<"meeb", 0xED17, any_fmul, FP32, z_load, 4>;
461-
defm MDB : BinaryRXEAndPseudo<"mdb", 0xED1C, any_fmul, FP64, z_load, 8>;
462-
defm MEEB : BinaryRXEAndPseudo<"meeb", 0xED17, any_fmul, FP32, z_fprload, 4>;
463-
defm MDB : BinaryRXEAndPseudo<"mdb", 0xED1C, any_fmul, FP64, z_fprload, 8>;
459+
defm MEEB : BinaryRXEAndPseudo<"meeb", 0xED17, z_any_fmul_noreassoc, FP32,
460+
z_load, 4>;
461+
defm MDB : BinaryRXEAndPseudo<"mdb", 0xED1C, z_any_fmul_noreassoc, FP64,
462+
z_load, 8>;
464463
}
465464

466465
// f64 multiplication of two FP32 registers.
@@ -502,12 +501,10 @@ let Uses = [FPC], mayRaiseFPException = 1 in {
502501
def MAEBR : TernaryRRD<"maebr", 0xB30E, z_any_fma, FP32, FP32>;
503502
def MADBR : TernaryRRD<"madbr", 0xB31E, z_any_fma, FP64, FP64>;
504503

505-
defm MAEB : TernaryRXFAndPseudo<"maeb", 0xED0E, z_any_fma, FP32, FP32, z_load, 4>;
506-
defm MADB : TernaryRXFAndPseudo<"madb", 0xED1E, z_any_fma, FP64, FP64, z_load, 8>;
507-
defm MAEB : TernaryRXFAndPseudo<"maeb", 0xED0E, z_any_fma, FP32, FP32,
508-
z_fprload, 4>;
509-
defm MADB : TernaryRXFAndPseudo<"madb", 0xED1E, z_any_fma, FP64, FP64,
510-
z_fprload, 8>;
504+
defm MAEB : TernaryRXFAndPseudo<"maeb", 0xED0E, z_any_fma_noreassoc, FP32,
505+
FP32, z_load, 4>;
506+
defm MADB : TernaryRXFAndPseudo<"madb", 0xED1E, z_any_fma_noreassoc, FP64,
507+
FP64, z_load, 8>;
511508
}
512509

513510
// Fused multiply-subtract.
@@ -517,10 +514,6 @@ let Uses = [FPC], mayRaiseFPException = 1 in {
517514

518515
defm MSEB : TernaryRXFAndPseudo<"mseb", 0xED0F, z_any_fms, FP32, FP32, z_load, 4>;
519516
defm MSDB : TernaryRXFAndPseudo<"msdb", 0xED1F, z_any_fms, FP64, FP64, z_load, 8>;
520-
defm MSEB : TernaryRXFAndPseudo<"mseb", 0xED0F, z_any_fms, FP32, FP32,
521-
z_fprload, 4>;
522-
defm MSDB : TernaryRXFAndPseudo<"msdb", 0xED1F, z_any_fms, FP64, FP64,
523-
z_fprload, 8>;
524517
}
525518

526519
// Division.
@@ -531,8 +524,6 @@ let Uses = [FPC], mayRaiseFPException = 1 in {
531524

532525
defm DEB : BinaryRXEAndPseudo<"deb", 0xED0D, any_fdiv, FP32, z_load, 4>;
533526
defm DDB : BinaryRXEAndPseudo<"ddb", 0xED1D, any_fdiv, FP64, z_load, 8>;
534-
defm DEB : BinaryRXEAndPseudo<"deb", 0xED0D, any_fdiv, FP32, z_fprload, 4>;
535-
defm DDB : BinaryRXEAndPseudo<"ddb", 0xED1D, any_fdiv, FP64, z_fprload, 8>;
536527
}
537528

538529
// Divide to integer.
@@ -552,8 +543,6 @@ let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC], CCValues = 0xF in {
552543

553544
def CEB : CompareRXE<"ceb", 0xED09, z_any_fcmp, FP32, z_load, 4>;
554545
def CDB : CompareRXE<"cdb", 0xED19, z_any_fcmp, FP64, z_load, 8>;
555-
def CEB : CompareRXE<"ceb", 0xED09, z_any_fcmp, FP32, z_fprload, 4>;
556-
def CDB : CompareRXE<"cdb", 0xED19, z_any_fcmp, FP64, z_fprload, 8>;
557546

558547
def KEBR : CompareRRE<"kebr", 0xB308, z_strict_fcmps, FP32, FP32>;
559548
def KDBR : CompareRRE<"kdbr", 0xB318, z_strict_fcmps, FP64, FP64>;

‎llvm/lib/Target/SystemZ/SystemZInstrFormats.td

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5539,29 +5539,31 @@ multiclass StringRRE<string mnemonic, bits<16> opcode,
55395539

55405540
multiclass BinaryVRRcAndCCPseudo<string mnemonic, bits<16> opcode,
55415541
SDPatternOperator operator,
5542+
SDPatternOperator reassoc_operator,
55425543
TypedReg tr1, TypedReg tr2, bits<4> type = 0,
55435544
bits<4> m5 = 0, bits<4> m6 = 0,
55445545
string fp_mnemonic = ""> {
5545-
def "" : BinaryVRRc<mnemonic, opcode, null_frag, tr1, tr2, type, m5, m6,
5546+
def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, m5, m6,
55465547
fp_mnemonic>;
5547-
let Defs = [CC] in
5548+
let Defs = [CC], AddedComplexity = 1 in // Win over "".
55485549
def _CCPseudo : Pseudo<(outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
55495550
[(set (tr1.vt tr1.op:$V1),
5550-
(operator (tr2.vt tr2.op:$V2),
5551-
(tr2.vt tr2.op:$V3)))]>;
5551+
(reassoc_operator (tr2.vt tr2.op:$V2),
5552+
(tr2.vt tr2.op:$V3)))]>;
55525553
}
55535554

55545555
multiclass TernaryVRReAndCCPseudo<string mnemonic, bits<16> opcode,
55555556
SDPatternOperator operator,
5557+
SDPatternOperator reassoc_operator,
55565558
TypedReg tr1, TypedReg tr2, bits<4> m5 = 0,
55575559
bits<4> type = 0, string fp_mnemonic = ""> {
5558-
def "" : TernaryVRRe<mnemonic, opcode, null_frag, tr1, tr2, m5, type,
5560+
def "" : TernaryVRRe<mnemonic, opcode, operator, tr1, tr2, m5, type,
55595561
fp_mnemonic>;
5560-
let Defs = [CC] in
5562+
let Defs = [CC], AddedComplexity = 1 in // Win over "".
55615563
def _CCPseudo : Pseudo<(outs tr1.op:$V1),
55625564
(ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
55635565
[(set (tr1.vt tr1.op:$V1),
5564-
(operator (tr2.vt tr2.op:$V2),
5565-
(tr2.vt tr2.op:$V3),
5566-
(tr1.vt tr1.op:$V4)))]>;
5566+
(reassoc_operator (tr2.vt tr2.op:$V2),
5567+
(tr2.vt tr2.op:$V3),
5568+
(tr1.vt tr1.op:$V4)))]>;
55675569
}

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