Address review comments

Author: mshockwave

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -22,7 +22,6 @@
 #include "LegalizeTypes.h"
 #include "llvm/ADT/SmallBitVector.h"
 #include "llvm/Analysis/MemoryLocation.h"
-#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/Analysis/VectorUtils.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -6957,32 +6956,14 @@ SDValue DAGTypeLegalizer::WidenVecOp_VSELECT(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::WidenVecOp_VP_CttzElements(SDNode *N) {
-  // Widen the result bit width if needed.
   SDLoc DL(N);
-  EVT OrigResVT = N->getValueType(0);
-  const Function &F = DAG.getMachineFunction().getFunction();
-
   SDValue Source = GetWidenedVector(N->getOperand(0));
   EVT SrcVT = Source.getValueType();
   SDValue Mask =
       GetWidenedMask(N->getOperand(1), SrcVT.getVectorElementCount());
 
-  // Compute the number of bits that can fit the result.
-  ConstantRange CR(APInt(64, SrcVT.getVectorMinNumElements()));
-  if (SrcVT.isScalableVT())
-    CR = CR.umul_sat(getVScaleRange(&F, 64));
-  // If the zero-is-poison flag is set in the original intrinsic, we can
-  // assume the upper limit of the result is EVL - 1.
-  if (N->getOpcode() == ISD::VP_CTTZ_ELTS_ZERO_UNDEF)
-    CR = CR.subtract(APInt(64, 1));
-
-  unsigned NewResWidth = OrigResVT.getScalarSizeInBits();
-  NewResWidth = std::min(NewResWidth, unsigned(CR.getActiveBits()));
-  NewResWidth = std::max(llvm::bit_ceil(NewResWidth), 8U);
-
-  EVT NewResVT = EVT::getIntegerVT(*DAG.getContext(), NewResWidth);
-  return DAG.getNode(N->getOpcode(), DL, NewResVT, Source, Mask,
-                     N->getOperand(2));
+  return DAG.getNode(N->getOpcode(), DL, N->getValueType(0),
+                     {Source, Mask, N->getOperand(2)}, N->getFlags());
 }
 
 //===----------------------------------------------------------------------===//

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

@@ -9095,7 +9095,8 @@ SDValue TargetLowering::expandVPCTTZElements(SDNode *N,
     SDValue AllZero = DAG.getConstant(0, DL, SrcVT);
     SrcVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
                              SrcVT.getVectorElementCount());
-    Source = DAG.getSetCC(DL, SrcVT, Source, AllZero, ISD::SETNE);
+    Source = DAG.getNode(ISD::VP_SETCC, DL, SrcVT, Source, AllZero,
+                         DAG.getCondCode(ISD::SETNE), Mask, EVL);
   }
 
   SDValue ExtEVL = DAG.getZExtOrTrunc(EVL, DL, ResVT);

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -5378,8 +5378,7 @@ SDValue RISCVTargetLowering::lowerVPCttzElements(SDValue Op,
   // Convert -1 to VL.
   SDValue SetCC =
       DAG.getSetCC(DL, XLenVT, Res, DAG.getConstant(0, DL, XLenVT), ISD::SETLT);
-  Res = DAG.getSelect(DL, XLenVT, SetCC, DAG.getZExtOrTrunc(EVL, DL, XLenVT),
-                      Res);
+  Res = DAG.getSelect(DL, XLenVT, SetCC, EVL, Res);
   return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Res);
 }