Skip to content

Commit acc8cbd

Browse files
realqhcrealqhc
committed
remove unnecessary cv.min/max, move XCV builtins into RISCV namespace
1 parent 824b9ba commit acc8cbd

File tree

10 files changed

+109
-102
lines changed

10 files changed

+109
-102
lines changed

‎clang/include/clang/Basic/BuiltinsRISCV.td

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,3 +146,8 @@ let Features = "zihintntl", Attributes = [CustomTypeChecking] in {
146146
def ntl_load : RISCVBuiltin<"void(...)">;
147147
def ntl_store : RISCVBuiltin<"void(...)">;
148148
} // Features = "zihintntl", Attributes = [CustomTypeChecking]
149+
150+
//===----------------------------------------------------------------------===//
151+
// XCV extensions.
152+
//===----------------------------------------------------------------------===//
153+
include "clang/Basic/BuiltinsRISCVXCV.td"

‎clang/include/clang/Basic/BuiltinsRISCVXCV.def

Lines changed: 0 additions & 41 deletions
This file was deleted.

‎clang/include/clang/Basic/BuiltinsRISCVXCV.td

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,43 @@
1+
//==- BuiltinsRISCVXCV.td - RISC-V CORE-V Builtin database ----*- C++ -*-==//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This file defines the CORE-V-specific builtin function database. Users of
10+
// this file must define the BUILTIN macro to make use of this information.
11+
//
12+
//===----------------------------------------------------------------------===//
13+
14+
class RISCXCVBuiltin<string prototype, string features = ""> : TargetBuiltin {
15+
let Spellings = ["__builtin_riscv_cv_" # NAME];
16+
let Prototype = prototype;
17+
let Features = features;
18+
}
19+
20+
let Attributes = [NoThrow, Const] in {
21+
//===----------------------------------------------------------------------===//
22+
// XCValu extension.
23+
//===----------------------------------------------------------------------===//
24+
def alu_slet : RISCXCVBuiltin<"int(int, int)", "xcvalu">;
25+
def alu_sletu : RISCXCVBuiltin<"int(unsigned int, unsigned int)", "xcvalu">;
26+
def alu_minu : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int)", "xcvalu">;
27+
def alu_maxu : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int)", "xcvalu">;
28+
def alu_exths : RISCXCVBuiltin<"int(int)", "xcvalu">;
29+
def alu_exthz : RISCXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">;
30+
def alu_extbs : RISCXCVBuiltin<"int(int)", "xcvalu">;
31+
def alu_extbz : RISCXCVBuiltin<"unsigned int(unsigned int)", "xcvalu">;
32+
33+
def alu_clip : RISCXCVBuiltin<"int(int, int)", "xcvalu">;
34+
def alu_clipu : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int)", "xcvalu">;
35+
def alu_addN : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
36+
def alu_adduN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, unsigned int)", "xcvalu">;
37+
def alu_addRN : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
38+
def alu_adduRN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, unsigned int)", "xcvalu">;
39+
def alu_subN : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
40+
def alu_subuN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, unsigned int)", "xcvalu">;
41+
def alu_subRN : RISCXCVBuiltin<"int(int, int, unsigned int)", "xcvalu">;
42+
def alu_subuRN : RISCXCVBuiltin<"unsigned int(unsigned int, unsigned int, unsigned int)", "xcvalu">;
43+
} // Attributes = [NoThrow, Const]

‎clang/include/clang/Basic/TargetBuiltins.h

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -152,22 +152,12 @@ namespace clang {
152152
};
153153
}
154154

155-
namespace RISCVXCV {
156-
enum {
157-
LastRVVBuiltin = RISCVVector::FirstTSBuiltin - 1,
158-
#define BUILTIN(ID, TYPE, ATTRS) BI__builtin_riscv_cv_##ID,
159-
#include "clang/Basic/BuiltinsRISCVXCV.def"
160-
FirstTSBuiltin,
161-
};
162-
} // namespace RISCVXCV
163-
164155
/// RISCV builtins
165156
namespace RISCV {
166157
enum {
167158
LastTIBuiltin = clang::Builtin::FirstTSBuiltin - 1,
168159
FirstRVVBuiltin = clang::Builtin::FirstTSBuiltin,
169160
LastRVVBuiltin = RISCVVector::FirstTSBuiltin - 1,
170-
LastXCVBuiltin = RISCVXCV::FirstTSBuiltin - 1,
171161
#define BUILTIN(ID, TYPE, ATTRS) BI##ID,
172162
#include "clang/Basic/BuiltinsRISCV.inc"
173163
LastTSBuiltin

‎clang/include/module.modulemap

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,6 @@ module Clang_Basic {
5555
textual header "clang/Basic/BuiltinsNEON.def"
5656
textual header "clang/Basic/BuiltinsNVPTX.def"
5757
textual header "clang/Basic/BuiltinsPPC.def"
58-
textual header "clang/Basic/BuiltinsRISCVXCV.def"
5958
textual header "clang/Basic/BuiltinsRISCVVector.def"
6059
textual header "clang/Basic/BuiltinsSME.def"
6160
textual header "clang/Basic/BuiltinsSVE.def"

‎clang/lib/Basic/Targets/RISCV.cpp

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -233,14 +233,7 @@ static constexpr Builtin::Info BuiltinInfo[] = {
233233
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
234234
#include "clang/Basic/BuiltinsRISCVVector.def"
235235
#define BUILTIN(ID, TYPE, ATTRS) \
236-
{"__builtin_riscv_cv_" #ID, TYPE, ATTRS, nullptr, \
237-
HeaderDesc::NO_HEADER, ALL_LANGUAGES},
238-
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
239-
{"__builtin_riscv_cv_" #ID, TYPE, ATTRS, FEATURE, \
240-
HeaderDesc::NO_HEADER, ALL_LANGUAGES},
241-
#include "clang/Basic/BuiltinsRISCVXCV.def"
242-
#define BUILTIN(ID, TYPE, ATTRS) \
243-
\ {#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
236+
{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
244237
#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
245238
{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
246239
#include "clang/Basic/BuiltinsRISCV.inc"

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 56 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -22426,15 +22426,63 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
2242622426

2242722427
return Store;
2242822428
}
22429+
// XCValu
22430+
case RISCV::BI__builtin_riscv_cv_alu_addN:
22431+
ID = Intrinsic::riscv_cv_alu_addN;
22432+
break;
22433+
case RISCV::BI__builtin_riscv_cv_alu_addRN:
22434+
ID = Intrinsic::riscv_cv_alu_addRN;
22435+
break;
22436+
case RISCV::BI__builtin_riscv_cv_alu_adduN:
22437+
ID = Intrinsic::riscv_cv_alu_adduN;
22438+
break;
22439+
case RISCV::BI__builtin_riscv_cv_alu_adduRN:
22440+
ID = Intrinsic::riscv_cv_alu_adduRN;
22441+
break;
22442+
case RISCV::BI__builtin_riscv_cv_alu_clip:
22443+
ID = Intrinsic::riscv_cv_alu_clip;
22444+
break;
22445+
case RISCV::BI__builtin_riscv_cv_alu_clipu:
22446+
ID = Intrinsic::riscv_cv_alu_clipu;
22447+
break;
22448+
case RISCV::BI__builtin_riscv_cv_alu_extbs:
22449+
ID = Intrinsic::riscv_cv_alu_extbs;
22450+
break;
22451+
case RISCV::BI__builtin_riscv_cv_alu_extbz:
22452+
ID = Intrinsic::riscv_cv_alu_extbz;
22453+
break;
22454+
case RISCV::BI__builtin_riscv_cv_alu_exths:
22455+
ID = Intrinsic::riscv_cv_alu_exths;
22456+
break;
22457+
case RISCV::BI__builtin_riscv_cv_alu_exthz:
22458+
ID = Intrinsic::riscv_cv_alu_exthz;
22459+
break;
22460+
case RISCV::BI__builtin_riscv_cv_alu_maxu:
22461+
ID = Intrinsic::riscv_cv_alu_maxu;
22462+
break;
22463+
case RISCV::BI__builtin_riscv_cv_alu_minu:
22464+
ID = Intrinsic::riscv_cv_alu_minu;
22465+
break;
22466+
case RISCV::BI__builtin_riscv_cv_alu_slet:
22467+
ID = Intrinsic::riscv_cv_alu_slet;
22468+
break;
22469+
case RISCV::BI__builtin_riscv_cv_alu_sletu:
22470+
ID = Intrinsic::riscv_cv_alu_sletu;
22471+
break;
22472+
case RISCV::BI__builtin_riscv_cv_alu_subN:
22473+
ID = Intrinsic::riscv_cv_alu_subN;
22474+
break;
22475+
case RISCV::BI__builtin_riscv_cv_alu_subRN:
22476+
ID = Intrinsic::riscv_cv_alu_subRN;
22477+
break;
22478+
case RISCV::BI__builtin_riscv_cv_alu_subuN:
22479+
ID = Intrinsic::riscv_cv_alu_subuN;
22480+
break;
22481+
case RISCV::BI__builtin_riscv_cv_alu_subuRN:
22482+
ID = Intrinsic::riscv_cv_alu_subuRN;
22483+
break;
2242922484

22430-
// Core-V
22431-
#define BUILTIN(NAME, TYPE, ATTRS) \
22432-
case RISCVXCV::BI__builtin_riscv_cv_##NAME: \
22433-
ID = Intrinsic::riscv_cv_##NAME; \
22434-
return Builder.CreateCall(CGM.getIntrinsic(ID), Ops);
22435-
#include "clang/Basic/BuiltinsRISCVXCV.def"
22436-
22437-
// Vector builtins are handled from here.
22485+
// Vector builtins are handled from here.
2243822486
#include "clang/Basic/riscv_vector_builtin_cg.inc"
2243922487
// SiFive Vector builtins are handled from here.
2244022488
#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"

‎clang/lib/Headers/riscv_corev_alu.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ __riscv_cv_alu_sletu(unsigned long a, unsigned long b) {
3434
}
3535

3636
static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_min(long a, long b) {
37-
return __builtin_riscv_cv_alu_min(a, b);
37+
return min(a, b);
3838
}
3939

4040
static __inline__ unsigned long __DEFAULT_FN_ATTRS
@@ -43,7 +43,7 @@ __riscv_cv_alu_minu(unsigned long a, unsigned long b) {
4343
}
4444

4545
static __inline__ long __DEFAULT_FN_ATTRS __riscv_cv_alu_max(long a, long b) {
46-
return __builtin_riscv_cv_alu_max(a, b);
46+
return max(a, b);
4747
}
4848

4949
static __inline__ unsigned long __DEFAULT_FN_ATTRS

‎clang/test/CodeGen/RISCV/riscv-xcvalu-c-api.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ int test_alu_sletu(uint32_t a, uint32_t b) {
1818
}
1919

2020
// CHECK-LABEL: @test_alu_min
21-
// CHECK: @llvm.riscv.cv.alu.min
21+
// CHECK: @min
2222
int test_alu_min(int32_t a, int32_t b) {
2323
return __riscv_cv_alu_min(a, b);
2424
}
@@ -30,7 +30,7 @@ int test_alu_minu(uint32_t a, uint32_t b) {
3030
}
3131

3232
// CHECK-LABEL: @test_alu_max
33-
// CHECK: @llvm.riscv.cv.alu.max
33+
// CHECK: @max
3434
int test_alu_max(int32_t a, int32_t b) {
3535
return __riscv_cv_alu_max(a, b);
3636
}

‎clang/test/CodeGen/RISCV/riscv-xcvalu.c

Lines changed: 0 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -46,21 +46,6 @@ int test_alu_sletu(uint32_t a, uint32_t b) {
4646
return __builtin_riscv_cv_alu_sletu(a, b);
4747
}
4848

49-
// CHECK-LABEL: @test_alu_min(
50-
// CHECK-NEXT: entry:
51-
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
52-
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
53-
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
54-
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
55-
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
56-
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
57-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.min(i32 [[TMP0]], i32 [[TMP1]])
58-
// CHECK-NEXT: ret i32 [[TMP2]]
59-
//
60-
int test_alu_min(int32_t a, int32_t b) {
61-
return __builtin_riscv_cv_alu_min(a, b);
62-
}
63-
6449
// CHECK-LABEL: @test_alu_minu(
6550
// CHECK-NEXT: entry:
6651
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
@@ -76,21 +61,6 @@ int test_alu_minu(uint32_t a, uint32_t b) {
7661
return __builtin_riscv_cv_alu_minu(a, b);
7762
}
7863

79-
// CHECK-LABEL: @test_alu_max(
80-
// CHECK-NEXT: entry:
81-
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
82-
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
83-
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
84-
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
85-
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
86-
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[B_ADDR]], align 4
87-
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.cv.alu.max(i32 [[TMP0]], i32 [[TMP1]])
88-
// CHECK-NEXT: ret i32 [[TMP2]]
89-
//
90-
int test_alu_max(int32_t a, int32_t b) {
91-
return __builtin_riscv_cv_alu_max(a, b);
92-
}
93-
9464
// CHECK-LABEL: @test_alu_maxu(
9565
// CHECK-NEXT: entry:
9666
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4

0 commit comments

Comments
 (0)