@@ -104,14 +104,18 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved (getNumRegs ());
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auto &Subtarget = MF.getSubtarget <RISCVSubtarget>();
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- // Mark any registers requested to be reserved as such
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- for (size_t Reg = 0 ; Reg < getNumRegs (); Reg++) {
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- if (Subtarget.isRegisterReservedByUser (Reg))
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+ for (Register Reg = RISCV::NoRegister; Reg < RISCV::NUM_TARGET_REGS; Reg++) {
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+ // Mark any GPRs requested to be reserved as such
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+ if (Reg >= RISCV::X0 && Reg <= RISCV::X31 &&
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+ Subtarget.isRegisterReservedByUser (Reg))
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+ markSuperRegs (Reserved, Reg);
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+
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+ // Mark all the registers defined as constant in TableGen as reserved.
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+ if (isConstantPhysReg (Reg))
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markSuperRegs (Reserved, Reg);
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}
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// Use markSuperRegs to ensure any register aliases are also reserved
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- markSuperRegs (Reserved, RISCV::X0); // zero
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markSuperRegs (Reserved, RISCV::X2); // sp
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markSuperRegs (Reserved, RISCV::X3); // gp
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markSuperRegs (Reserved, RISCV::X4); // tp
@@ -136,7 +140,6 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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markSuperRegs (Reserved, RISCV::VTYPE);
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markSuperRegs (Reserved, RISCV::VXSAT);
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markSuperRegs (Reserved, RISCV::VXRM);
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- markSuperRegs (Reserved, RISCV::VLENB); // vlenb (constant)
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// Floating point environment registers.
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markSuperRegs (Reserved, RISCV::FRM);
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