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[MLIR][SPIRV] Add definition for SPV_INTEL_split_barrier ops (#115738)
The [`SPV_INTEL_split_barrier` extension](https://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_split_barrier.html) defines operations to split control barrier semantics in two operations. Add support for these operations (arrive and wait) to the dialect. Signed-off-by: Victor Perez <[email protected]>
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‎mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4512,6 +4512,8 @@ def SPIRV_OC_OpAssumeTrueKHR : I32EnumAttrCase<"OpAssumeTrueKHR",
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def SPIRV_OC_OpAtomicFAddEXT : I32EnumAttrCase<"OpAtomicFAddEXT", 6035>;
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def SPIRV_OC_OpConvertFToBF16INTEL : I32EnumAttrCase<"OpConvertFToBF16INTEL", 6116>;
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def SPIRV_OC_OpConvertBF16ToFINTEL : I32EnumAttrCase<"OpConvertBF16ToFINTEL", 6117>;
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def SPIRV_OC_OpControlBarrierArriveINTEL : I32EnumAttrCase<"OpControlBarrierArriveINTEL", 6142>;
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def SPIRV_OC_OpControlBarrierWaitINTEL : I32EnumAttrCase<"OpControlBarrierWaitINTEL", 6143>;
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def SPIRV_OC_OpGroupIMulKHR : I32EnumAttrCase<"OpGroupIMulKHR", 6401>;
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def SPIRV_OC_OpGroupFMulKHR : I32EnumAttrCase<"OpGroupFMulKHR", 6402>;
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@@ -4602,7 +4604,9 @@ def SPIRV_OpcodeAttr :
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SPIRV_OC_OpCooperativeMatrixLengthKHR, SPIRV_OC_OpSubgroupBlockReadINTEL,
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SPIRV_OC_OpSubgroupBlockWriteINTEL, SPIRV_OC_OpAssumeTrueKHR,
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SPIRV_OC_OpAtomicFAddEXT, SPIRV_OC_OpConvertFToBF16INTEL,
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SPIRV_OC_OpConvertBF16ToFINTEL, SPIRV_OC_OpGroupIMulKHR,
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SPIRV_OC_OpConvertBF16ToFINTEL,
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SPIRV_OC_OpControlBarrierArriveINTEL, SPIRV_OC_OpControlBarrierWaitINTEL,
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SPIRV_OC_OpGroupIMulKHR,
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SPIRV_OC_OpGroupFMulKHR
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]>;
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‎mlir/include/mlir/Dialect/SPIRV/IR/SPIRVIntelExtOps.td

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Original file line numberDiff line numberDiff line change
@@ -111,6 +111,95 @@ def SPIRV_INTELConvertBF16ToFOp : SPIRV_IntelVendorOp<"ConvertBF16ToF", []> {
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}
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// -----
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class SPIRV_IntelSplitBarrierOp<string mnemonic>
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: SPIRV_IntelVendorOp<mnemonic, []> {
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let availability = [
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MinVersion<SPIRV_V_1_0>,
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MaxVersion<SPIRV_V_1_6>,
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Extension<[SPV_INTEL_split_barrier]>,
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Capability<[SPIRV_C_SplitBarrierINTEL]>
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];
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let arguments = (ins
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SPIRV_ScopeAttr:$execution_scope,
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SPIRV_ScopeAttr:$memory_scope,
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SPIRV_MemorySemanticsAttr:$memory_semantics
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);
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let results = (outs);
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let assemblyFormat = [{
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$execution_scope `,` $memory_scope `,` $memory_semantics attr-dict
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}];
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let hasVerifier = 0;
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}
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def SPIRV_INTELControlBarrierArriveOp
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: SPIRV_IntelSplitBarrierOp<"ControlBarrierArrive"> {
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let summary = "See extension SPV_INTEL_split_barrier";
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let description = [{
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Indicates that an invocation has arrived at a split control barrier. This
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may allow other invocations waiting on the split control barrier to continue
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executing.
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When `Execution` is `Workgroup` or larger, behavior is undefined unless all
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invocations within `Execution` execute the same dynamic instance of this
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instruction. When `Execution` is `Subgroup` or `Invocation`, the behavior of
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this instruction in non-uniform control flow is defined by the client API.
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If `Semantics` is not `None`, this instruction also serves as the start of a
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memory barrier similar to an `OpMemoryBarrier` instruction with the same
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`Memory` and `Semantics` operands. This allows atomically specifying both a
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control barrier and a memory barrier (that is, without needing two
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instructions). If `Semantics` is `None`, `Memory` is ignored.
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#### Example:
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```mlir
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spirv.ControlBarrierArrive <Workgroup>, <Device>, <Acquire|UniformMemory>
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```
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}];
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}
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// -----
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def SPIRV_INTELControlBarrierWaitOp
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: SPIRV_IntelSplitBarrierOp<"ControlBarrierWait"> {
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let summary = "See extension SPV_INTEL_split_barrier";
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let description = [{
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Waits for other invocations of this module to arrive at a split control
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barrier.
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When `Execution` is `Workgroup` or larger, behavior is undefined unless all
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invocations within `Execution` execute the same dynamic instance of this
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instruction. When `Execution` is `Subgroup` or `Invocation`, the behavior of
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this instruction in non-uniform control flow is defined by the client API.
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If `Semantics` is not `None`, this instruction also serves as the end of a
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memory barrier similar to an `OpMemoryBarrier` instruction with the same
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`Memory` and `Semantics` operands. This ensures that memory accesses issued
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before arriving at the split barrier are observed before memory accesses
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issued after this instruction. This control is ensured only for memory
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accesses issued by this invocation and observed by another invocation
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executing within `Memory` scope. This allows atomically specifying both a
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control barrier and a memory barrier (that is, without needing two
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instructions). If `Semantics` is `None`, `Memory` is ignored.
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#### Example:
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```mlir
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spirv.ControlBarrierWait <Workgroup>, <Device>, <Acquire|UniformMemory>
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```
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}];
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}
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// -----
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#endif // MLIR_DIALECT_SPIRV_IR_INTEL_EXT_OPS

‎mlir/test/Dialect/SPIRV/IR/intel-ext-ops.mlir

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,20 @@ spirv.func @bf16_to_f32_vec_unsupported(%arg0 : vector<2xi16>) "None" {
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// -----
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//===----------------------------------------------------------------------===//
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// spirv.INTEL.SplitBarrier
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//===----------------------------------------------------------------------===//
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spirv.func @split_barrier() "None" {
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// CHECK: spirv.INTEL.ControlBarrierArrive <Workgroup>, <Device>, <Acquire|UniformMemory>
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spirv.INTEL.ControlBarrierArrive <Workgroup>, <Device>, <Acquire|UniformMemory>
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// CHECK: spirv.INTEL.ControlBarrierWait <Workgroup>, <Device>, <Acquire|UniformMemory>
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spirv.INTEL.ControlBarrierWait <Workgroup>, <Device>, <Acquire|UniformMemory>
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spirv.Return
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}
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// -----
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//===----------------------------------------------------------------------===//
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// spirv.INTEL.CacheControls
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//===----------------------------------------------------------------------===//

‎mlir/test/Target/SPIRV/intel-ext-ops.mlir

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,3 +29,21 @@ spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [Bfloat16ConversionINTEL]
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spirv.Return
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}
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}
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// -----
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//===----------------------------------------------------------------------===//
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// spirv.INTEL.SplitBarrier
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//===----------------------------------------------------------------------===//
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// CHECK: spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [SplitBarrierINTEL], [SPV_INTEL_split_barrier]>
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spirv.module Logical GLSL450 requires #spirv.vce<v1.0, [SplitBarrierINTEL], [SPV_INTEL_split_barrier]> {
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// CHECK-LABEL: @split_barrier
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spirv.func @split_barrier() "None" {
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// CHECK: spirv.INTEL.ControlBarrierArrive <Workgroup>, <Device>, <Acquire|UniformMemory>
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spirv.INTEL.ControlBarrierArrive <Workgroup>, <Device>, <Acquire|UniformMemory>
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// CHECK: spirv.INTEL.ControlBarrierWait <Workgroup>, <Device>, <Acquire|UniformMemory>
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spirv.INTEL.ControlBarrierWait <Workgroup>, <Device>, <Acquire|UniformMemory>
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spirv.Return
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}
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}

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