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[TableGen] Add support for DefaultMode in per-HwMode encode/decode. (#83029)
Currently the decoder and encoder emitters will crash if DefaultMode is used within an EncodingByHwMode. As can be done today for RegInfoByHwMode and ValueTypeByHwMode, this patch adds support for this usage in EncodingByHwMode: let EncodingInfos = EncodingByHwMode<[ModeA, DefaultMode], [EncA, EncDefault]>;
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‎llvm/test/TableGen/HwModeEncodeDecode3.td

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// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | \
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// RUN: FileCheck %s --check-prefix=ENCODER
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// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | \
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// RUN: FileCheck %s --check-prefix=DECODER
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// RUN: llvm-tblgen -gen-disassembler --suppress-per-hwmode-duplicates -I \
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// RUN: %p/../../include %s | FileCheck %s --check-prefix=DECODER-SUPPRESS
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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def Myi32 : Operand<i32> {
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let DecoderMethod = "DecodeMyi32";
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}
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def HasA : Predicate<"Subtarget->hasA()">;
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def HasB : Predicate<"Subtarget->hasB()">;
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def ModeA : HwMode<"+a", [HasA]>;
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def ModeB : HwMode<"+b", [HasB]>;
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def fooTypeEncDefault : InstructionEncoding {
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let Size = 8;
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field bits<64> SoftFail = 0;
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bits<64> Inst;
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bits<8> factor;
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let Inst{7...0} = factor;
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let Inst{3...2} = 0b10;
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let Inst{1...0} = 0b00;
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}
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def fooTypeEncA : InstructionEncoding {
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let Size = 4;
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field bits<32> SoftFail = 0;
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bits<32> Inst;
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bits<8> factor;
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let Inst{7...0} = factor;
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let Inst{3...2} = 0b11;
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let Inst{1...0} = 0b00;
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}
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def fooTypeEncB : InstructionEncoding {
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let Size = 4;
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field bits<32> SoftFail = 0;
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bits<32> Inst;
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bits<8> factor;
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let Inst{15...8} = factor;
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let Inst{1...0} = 0b11;
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}
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// Test for DefaultMode as a selector.
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def foo : Instruction {
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let OutOperandList = (outs);
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let InOperandList = (ins i32imm:$factor);
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let EncodingInfos = EncodingByHwMode<
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[ModeA, ModeB, DefaultMode], [fooTypeEncA, fooTypeEncB, fooTypeEncDefault]
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>;
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let AsmString = "foo $factor";
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}
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def bar: Instruction {
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let OutOperandList = (outs);
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let InOperandList = (ins i32imm:$factor);
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let Size = 4;
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bits<32> Inst;
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bits<32> SoftFail;
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bits<8> factor;
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let Inst{31...24} = factor;
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let Inst{1...0} = 0b10;
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let AsmString = "bar $factor";
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}
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def baz : Instruction {
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let OutOperandList = (outs);
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let InOperandList = (ins i32imm:$factor);
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bits<32> Inst;
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let EncodingInfos = EncodingByHwMode<
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[ModeB], [fooTypeEncA]
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>;
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let AsmString = "foo $factor";
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}
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def unrelated: Instruction {
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let OutOperandList = (outs);
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let DecoderNamespace = "Alt";
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let InOperandList = (ins i32imm:$factor);
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let Size = 4;
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bits<32> Inst;
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bits<32> SoftFail;
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bits<8> factor;
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let Inst{31...24} = factor;
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let Inst{1...0} = 0b10;
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let AsmString = "unrelated $factor";
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}
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// DECODER-LABEL: DecoderTableAlt_DefaultMode32[] =
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// DECODER-DAG: Opcode: unrelated
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// DECODER-LABEL: DecoderTableAlt_ModeA32[] =
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// DECODER-DAG: Opcode: unrelated
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// DECODER-LABEL: DecoderTableAlt_ModeB32[] =
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// DECODER-DAG: Opcode: unrelated
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// DECODER-LABEL: DecoderTable_DefaultMode32[] =
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// DECODER-DAG: Opcode: bar
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// DECODER-LABEL: DecoderTable_DefaultMode64[] =
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// DECODER-DAG: Opcode: fooTypeEncDefault:foo
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// DECODER-LABEL: DecoderTable_ModeA32[] =
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// DECODER-DAG: Opcode: fooTypeEncA:foo
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// DECODER-DAG: Opcode: bar
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// DECODER-LABEL: DecoderTable_ModeB32[] =
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// DECODER-DAG: Opcode: fooTypeEncB:foo
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// DECODER-DAG: Opcode: fooTypeEncA:baz
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// DECODER-DAG: Opcode: bar
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// DECODER-SUPPRESS-LABEL: DecoderTableAlt_AllModes32[] =
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// DECODER-SUPPRESS-DAG: Opcode: unrelated
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// DECODER-SUPPRESS-LABEL: DecoderTable_AllModes32[] =
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// DECODER-SUPPRESS-DAG: Opcode: bar
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// DECODER-SUPPRESS-LABEL: DecoderTable_DefaultMode64[] =
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// DECODER-SUPPRESS-NOT: Opcode: bar
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// DECODER-SUPPRESS-DAG: Opcode: fooTypeEncDefault:foo
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// DECODER-SUPPRESS-LABEL: DecoderTable_ModeA32[] =
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// DECODER-SUPPRESS-DAG: Opcode: fooTypeEncA:foo
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// DECODER-SUPPRESS-NOT: Opcode: bar
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// DECODER-SUPPRESS-LABEL: DecoderTable_ModeB32[] =
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// DECODER-SUPPRESS-DAG: Opcode: fooTypeEncB:foo
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// DECODER-SUPPRESS-DAG: Opcode: fooTypeEncA:baz
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// DECODER-SUPPRESS-NOT: Opcode: bar
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// ENCODER-LABEL: static const uint64_t InstBits_DefaultMode[] = {
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// ENCODER: UINT64_C(2), // bar
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// ENCODER: UINT64_C(0), // baz
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// ENCODER: UINT64_C(8), // foo
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// ENCODER: UINT64_C(2), // unrelated
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// ENCODER-LABEL: static const uint64_t InstBits_ModeA[] = {
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// ENCODER: UINT64_C(2), // bar
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// ENCODER: UINT64_C(0), // baz
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// ENCODER: UINT64_C(12), // foo
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// ENCODER: UINT64_C(2), // unrelated
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// ENCODER-LABEL: static const uint64_t InstBits_ModeB[] = {
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// ENCODER: UINT64_C(2), // bar
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// ENCODER: UINT64_C(12), // baz
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// ENCODER: UINT64_C(3), // foo
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// ENCODER: UINT64_C(2), // unrelated
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// ENCODER: unsigned HwMode = STI.getHwMode();
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// ENCODER: switch (HwMode) {
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// ENCODER: default: llvm_unreachable("Unknown hardware mode!"); break;
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// ENCODER: case 0: InstBits = InstBits_DefaultMode; break;
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// ENCODER: case 1: InstBits = InstBits_ModeA; break;
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// ENCODER: case 2: InstBits = InstBits_ModeB; break;
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// ENCODER: };
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// ENCODER: case ::foo: {
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// ENCODER: switch (HwMode) {
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// ENCODER: default: llvm_unreachable("Unhandled HwMode");
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// ENCODER: case 0: {
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// ENCODER: case 1: {
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// ENCODER: case 2: {
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‎llvm/utils/TableGen/CodeEmitterGen.cpp

Lines changed: 4 additions & 4 deletions
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@@ -365,8 +365,8 @@ void CodeEmitterGen::emitInstructionBaseValues(
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if (HwMode == -1)
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o << " static const uint64_t InstBits[] = {\n";
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else
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o << " static const uint64_t InstBits_" << HWM.getMode(HwMode).Name
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<< "[] = {\n";
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o << " static const uint64_t InstBits_"
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<< HWM.getModeName(HwMode, /*IncludeDefault=*/true) << "[] = {\n";
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for (const CodeGenInstruction *CGI : NumberedInstructions) {
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Record *R = CGI->TheDef;
@@ -495,8 +495,8 @@ void CodeEmitterGen::run(raw_ostream &o) {
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o << " switch (HwMode) {\n";
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o << " default: llvm_unreachable(\"Unknown hardware mode!\"); break;\n";
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for (unsigned I : HwModes) {
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o << " case " << I << ": InstBits = InstBits_" << HWM.getMode(I).Name
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<< "; break;\n";
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o << " case " << I << ": InstBits = InstBits_"
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<< HWM.getModeName(I, /*IncludeDefault=*/true) << "; break;\n";
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}
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o << " };\n";
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}

‎llvm/utils/TableGen/CodeGenHwModes.h

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@@ -52,6 +52,11 @@ struct CodeGenHwModes {
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assert(Id != 0 && "Mode id of 0 is reserved for the default mode");
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return Modes[Id - 1];
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}
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StringRef getModeName(unsigned Id, bool IncludeDefault = false) const {
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if (IncludeDefault && Id == CodeGenHwModes::DefaultMode)
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return DefaultModeName;
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return getMode(Id).Name;
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}
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const HwModeSelect &getHwModeSelect(Record *R) const;
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const std::map<Record *, HwModeSelect> &getHwModeSelects() const {
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return ModeSelects;

‎llvm/utils/TableGen/DecoderEmitter.cpp

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2461,8 +2461,9 @@ collectHwModesReferencedForEncodings(const CodeGenHwModes &HWM,
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BV.set(P.first);
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}
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}
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transform(BV.set_bits(), std::back_inserter(Names),
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[&HWM](const int &M) { return HWM.getMode(M).Name; });
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transform(BV.set_bits(), std::back_inserter(Names), [&HWM](const int &M) {
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return HWM.getModeName(M, /*IncludeDefault=*/true);
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});
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}
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// Emits disassembler code for instruction decoding.
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if (DefInit *DI = dyn_cast_or_null<DefInit>(RV->getValue())) {
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EncodingInfoByHwMode EBM(DI->getDef(), HWM);
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for (auto &KV : EBM)
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NumberedEncodings.emplace_back(KV.second, NumberedInstruction,
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HWM.getMode(KV.first).Name);
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NumberedEncodings.emplace_back(
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KV.second, NumberedInstruction,
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HWM.getModeName(KV.first, /*IncludeDefault=*/true));
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continue;
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}
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}

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