[llvm][PassSupport] don't require passes to be default constructible

Quite a few passes are not default constructible. In order to properly
support -{start|stop}-{before|after}= for these passes, we would like to
continue to use INITIALIZE_PASS, but not necessarily provide a default
constructor.

Delete the default constructors of classes derived from
SelectionDAGISel.

Link: #59538

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D140349

Author: nickdesaulniers

llvm/include/llvm/PassSupport.h

@@ -27,6 +27,7 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/PassInfo.h"
 #include "llvm/PassRegistry.h"
+#include "llvm/Support/Error.h"
 #include "llvm/Support/Threading.h"
 #include <functional>
 
@@ -77,7 +78,21 @@ class Pass;
   INITIALIZE_PASS_BEGIN(PassName, Arg, Name, Cfg, Analysis)                    \
   PassName::registerOptions();
 
-template <typename PassName> Pass *callDefaultCtor() { return new PassName(); }
+template <
+    class PassName,
+    std::enable_if_t<std::is_default_constructible<PassName>{}, bool> = true>
+Pass *callDefaultCtor() {
+  return new PassName();
+}
+
+template <
+    class PassName,
+    std::enable_if_t<!std::is_default_constructible<PassName>{}, bool> = true>
+Pass *callDefaultCtor() {
+  // Some codegen passes should only be testable via
+  // `llc -{start|stop}-{before|after}=<passname>`, not via `opt -<passname>`.
+  report_fatal_error("target-specific codegen-only pass");
+}
 
 //===---------------------------------------------------------------------------
 /// RegisterPass<t> template - This template class is used to notify the system

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -45,6 +45,8 @@ class AArch64DAGToDAGISel : public SelectionDAGISel {
 public:
   static char ID;
 
+  AArch64DAGToDAGISel() = delete;
+
   explicit AArch64DAGToDAGISel(AArch64TargetMachine &tm,
                                CodeGenOpt::Level OptLevel)
       : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr) {}

llvm/lib/Target/AMDGPU/AMDGPU.h

@@ -240,9 +240,8 @@ struct AMDGPUPromoteAllocaToVectorPass
 };
 
 Pass *createAMDGPUStructurizeCFGPass();
-FunctionPass *createAMDGPUISelDag(
-  TargetMachine *TM = nullptr,
-  CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
+FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
+                                  CodeGenOpt::Level OptLevel);
 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
 
 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

@@ -111,15 +111,14 @@ INITIALIZE_PASS_END(AMDGPUDAGToDAGISel, "amdgpu-isel",
 
 /// This pass converts a legalized DAG into a AMDGPU-specific
 // DAG, ready for instruction scheduling.
-FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
+FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM,
                                         CodeGenOpt::Level OptLevel) {
   return new AMDGPUDAGToDAGISel(TM, OptLevel);
 }
 
-AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(
-    TargetMachine *TM /*= nullptr*/,
-    CodeGenOpt::Level OptLevel /*= CodeGenOpt::Default*/)
-    : SelectionDAGISel(ID, *TM, OptLevel) {
+AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM,
+                                       CodeGenOpt::Level OptLevel)
+    : SelectionDAGISel(ID, TM, OptLevel) {
   EnableLateStructurizeCFG = AMDGPUTargetMachine::EnableLateStructurizeCFG;
 }
 

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h

@@ -93,8 +93,9 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
 public:
   static char ID;
 
-  explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr,
-                              CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
+  AMDGPUDAGToDAGISel() = delete;
+
+  explicit AMDGPUDAGToDAGISel(TargetMachine &TM, CodeGenOpt::Level OptLevel);
   ~AMDGPUDAGToDAGISel() override = default;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -1068,7 +1068,7 @@ bool AMDGPUPassConfig::addPreISel() {
 }
 
 bool AMDGPUPassConfig::addInstSelector() {
-  addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
+  addPass(createAMDGPUISelDag(getAMDGPUTargetMachine(), getOptLevel()));
   return false;
 }
 

llvm/lib/Target/AMDGPU/R600.h

@@ -27,7 +27,7 @@ FunctionPass *createR600ClauseMergePass();
 FunctionPass *createR600Packetizer();
 FunctionPass *createR600ControlFlowFinalizer();
 FunctionPass *createR600MachineCFGStructurizerPass();
-FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
+FunctionPass *createR600ISelDag(TargetMachine &TM, CodeGenOpt::Level OptLevel);
 ModulePass *createR600OpenCLImageTypeLoweringPass();
 
 void initializeR600ClauseMergePassPass(PassRegistry &);

llvm/lib/Target/AMDGPU/R600ISelDAGToDAG.cpp

@@ -27,7 +27,9 @@ class R600DAGToDAGISel : public AMDGPUDAGToDAGISel {
                                        SDValue &Offset);
 
 public:
-  explicit R600DAGToDAGISel(TargetMachine *TM, CodeGenOpt::Level OptLevel)
+  R600DAGToDAGISel() = delete;
+
+  explicit R600DAGToDAGISel(TargetMachine &TM, CodeGenOpt::Level OptLevel)
       : AMDGPUDAGToDAGISel(TM, OptLevel) {}
 
   void Select(SDNode *N) override;
@@ -178,7 +180,7 @@ bool R600DAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
 
 /// This pass converts a legalized DAG into a R600-specific
 // DAG, ready for instruction scheduling.
-FunctionPass *llvm::createR600ISelDag(TargetMachine *TM,
+FunctionPass *llvm::createR600ISelDag(TargetMachine &TM,
                                       CodeGenOpt::Level OptLevel) {
   return new R600DAGToDAGISel(TM, OptLevel);
 }

llvm/lib/Target/AMDGPU/R600TargetMachine.cpp

@@ -118,7 +118,7 @@ bool R600PassConfig::addPreISel() {
 }
 
 bool R600PassConfig::addInstSelector() {
-  addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel()));
+  addPass(createR600ISelDag(getAMDGPUTargetMachine(), getOptLevel()));
   return false;
 }
 

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

@@ -170,6 +170,8 @@ namespace {
   public:
     static char ID;
 
+    X86DAGToDAGISel() = delete;
+
     explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
         : SelectionDAGISel(ID, tm, OptLevel), Subtarget(nullptr),
           OptForMinSize(false), IndirectTlsSegRefs(false) {}