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[AMDGPU] Fix using wrong register in frame index shift (#101649)
In case of v_mad we have materialized the offset in vgpr and mad is performed in wave space, later vgpr have to be shifted back in lane space. [#99556](#99556) introduces a bug. Co-authored-by: Pankajdwivedi-25 <[email protected]>
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-7
lines changed

3 files changed

+7
-7
lines changed

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2591,7 +2591,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
25912591
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64),
25922592
TmpResultReg)
25932593
.addImm(ST.getWavefrontSizeLog2())
2594-
.addReg(FrameReg);
2594+
.addReg(TmpResultReg);
25952595
}
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25972597
Register NewDest = IsCopy ? ResultReg

llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -708,7 +708,7 @@ body: |
708708
; GFX8-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc
709709
; GFX8-NEXT: $vgpr0 = V_MOV_B32_e32 64, implicit $exec
710710
; GFX8-NEXT: $vgpr0 = V_MAD_U32_U24_e64 killed $vgpr0, 64, $sgpr32, 0, implicit $exec
711-
; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec
711+
; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $vgpr0, implicit $exec
712712
; GFX8-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
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; GFX8-NEXT: S_NOP 0, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
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; GFX8-NEXT: S_NOP 0, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
@@ -903,7 +903,7 @@ body: |
903903
; GFX8-NEXT: S_CMP_EQ_I32 $sgpr4, $sgpr5, implicit-def $scc
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; GFX8-NEXT: $vgpr0 = V_MOV_B32_e32 68, implicit $exec
905905
; GFX8-NEXT: $vgpr0 = V_MAD_U32_U24_e64 killed $vgpr0, 64, $sgpr32, 0, implicit $exec
906-
; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr32, implicit $exec
906+
; GFX8-NEXT: $vgpr0 = V_LSHRREV_B32_e64 6, $vgpr0, implicit $exec
907907
; GFX8-NEXT: $sgpr4 = V_READFIRSTLANE_B32 $vgpr0, implicit $exec
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; GFX8-NEXT: S_NOP 0, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
909909
; GFX8-NEXT: S_NOP 0, implicit $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15

llvm/test/CodeGen/AMDGPU/materialize-frame-index-sgpr.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
7777
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], s32
7878
; GFX7-NEXT: v_mov_b32_e32 v0, 0x4040
7979
; GFX7-NEXT: v_mad_u32_u24 v0, v0, 64, s32
80-
; GFX7-NEXT: v_lshr_b32_e64 v0, s32, 6
80+
; GFX7-NEXT: v_lshrrev_b32_e32 v0, 6, v0
8181
; GFX7-NEXT: v_writelane_b32 v23, s59, 28
8282
; GFX7-NEXT: v_readfirstlane_b32 s59, v0
8383
; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s32
@@ -168,7 +168,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs() #0
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; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], s32
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; GFX8-NEXT: v_mov_b32_e32 v0, 0x4040
170170
; GFX8-NEXT: v_mad_u32_u24 v0, v0, 64, s32
171-
; GFX8-NEXT: v_lshrrev_b32_e64 v0, 6, s32
171+
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 6, v0
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; GFX8-NEXT: v_writelane_b32 v23, s59, 28
173173
; GFX8-NEXT: v_readfirstlane_b32 s59, v0
174174
; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], s32
@@ -841,7 +841,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
841841
; GFX7-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
842842
; GFX7-NEXT: ;;#ASMEND
843843
; GFX7-NEXT: v_mad_u32_u24 v22, v22, 64, s32
844-
; GFX7-NEXT: v_lshr_b32_e64 v22, s32, 6
844+
; GFX7-NEXT: v_lshrrev_b32_e32 v22, 6, v22
845845
; GFX7-NEXT: v_writelane_b32 v21, s59, 28
846846
; GFX7-NEXT: v_readfirstlane_b32 s59, v22
847847
; GFX7-NEXT: ;;#ASMSTART
@@ -924,7 +924,7 @@ define void @scalar_mov_materializes_frame_index_no_live_scc_no_live_sgprs__lowe
924924
; GFX8-NEXT: ; def s[0:15], s[16:31], s[32:47], s[48:55], s[56:57], s58, v[0:15], v[16:20], vcc
925925
; GFX8-NEXT: ;;#ASMEND
926926
; GFX8-NEXT: v_mad_u32_u24 v22, v22, 64, s32
927-
; GFX8-NEXT: v_lshrrev_b32_e64 v22, 6, s32
927+
; GFX8-NEXT: v_lshrrev_b32_e32 v22, 6, v22
928928
; GFX8-NEXT: v_writelane_b32 v21, s59, 28
929929
; GFX8-NEXT: v_readfirstlane_b32 s59, v22
930930
; GFX8-NEXT: ;;#ASMSTART

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