Skip to content

Commit adff330

Browse files
NexMingNexMing
committed
Add testcases.
1 parent ed5f8f2 commit adff330

File tree

2 files changed

+143
-4
lines changed

2 files changed

+143
-4
lines changed

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vp-splice.ll

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -299,3 +299,60 @@ define <8 x half> @test_vp_splice_v8f16_masked(<8 x half> %va, <8 x half> %vb, <
299299
%v = call <8 x half> @llvm.experimental.vp.splice.v8f16(<8 x half> %va, <8 x half> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
300300
ret <8 x half> %v
301301
}
302+
303+
define <4 x i32> @test_vp_splice_v4i32_with_firstelt(i32 %first, <4 x i32> %vb, <4 x i1> %mask, i32 zeroext %evl) {
304+
; CHECK-LABEL: test_vp_splice_v4i32_with_firstelt:
305+
; CHECK: # %bb.0:
306+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
307+
; CHECK-NEXT: vmv.s.x v9, a0
308+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
309+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
310+
; CHECK-NEXT: vmv.v.v v8, v9
311+
; CHECK-NEXT: ret
312+
%va = insertelement <4 x i32> poison, i32 %first, i32 0
313+
%v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %va, <4 x i32> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
314+
ret <4 x i32> %v
315+
}
316+
317+
define <4 x i32> @test_vp_splice_v4i32_with_splat_firstelt(i32 %first, <4 x i32> %vb, <4 x i1> %mask, i32 zeroext %evl) {
318+
; CHECK-LABEL: test_vp_splice_v4i32_with_splat_firstelt:
319+
; CHECK: # %bb.0:
320+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
321+
; CHECK-NEXT: vmv.v.x v9, a0
322+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
323+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
324+
; CHECK-NEXT: vmv.v.v v8, v9
325+
; CHECK-NEXT: ret
326+
%ins = insertelement <4 x i32> poison, i32 %first, i32 0
327+
%splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer
328+
%v = call <4 x i32> @llvm.experimental.vp.splice.v4i32(<4 x i32> %splat, <4 x i32> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
329+
ret <4 x i32> %v
330+
}
331+
332+
define <4 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <4 x float> %vb, <4 x i1> %mask, i32 zeroext %evl) {
333+
; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
334+
; CHECK: # %bb.0:
335+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
336+
; CHECK-NEXT: vfmv.s.f v9, fa0
337+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
338+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
339+
; CHECK-NEXT: vmv.v.v v8, v9
340+
; CHECK-NEXT: ret
341+
%va = insertelement <4 x float> poison, float %first, i32 0
342+
%v = call <4 x float> @llvm.experimental.vp.splice.nxv2f32(<4 x float> %va, <4 x float> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
343+
ret <4 x float> %v
344+
}
345+
346+
define <4 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <4 x half> %vb, <4 x i1> %mask, i32 zeroext %evl) {
347+
; CHECK-LABEL: test_vp_splice_nxv2f16_with_firstelt:
348+
; CHECK: # %bb.0:
349+
; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma
350+
; CHECK-NEXT: vfmv.s.f v9, fa0
351+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
352+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
353+
; CHECK-NEXT: vmv1r.v v8, v9
354+
; CHECK-NEXT: ret
355+
%va = insertelement <4 x half> poison, half %first, i32 0
356+
%v = call <4 x half> @llvm.experimental.vp.splice.nxv2f16(<4 x half> %va, <4 x half> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
357+
ret <4 x half> %v
358+
}

‎llvm/test/CodeGen/RISCV/rvv/vp-splice.ll

Lines changed: 86 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zvfh,+zvfbfmin -verify-machineinstrs \
3-
; RUN: < %s | FileCheck %s
4-
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zvfhmin,+zvfbfmin -verify-machineinstrs \
5-
; RUN: < %s | FileCheck %s
2+
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfh,+zvfbfmin -verify-machineinstrs \
3+
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
4+
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfhmin,+zvfbfmin -verify-machineinstrs \
5+
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
66

77
define <vscale x 2 x i64> @test_vp_splice_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
88
; CHECK-LABEL: test_vp_splice_nxv2i64:
@@ -505,3 +505,85 @@ define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_masked(<vscale x 2 x bfloa
505505
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
506506
ret <vscale x 2 x bfloat> %v
507507
}
508+
509+
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
510+
; CHECK-LABEL: test_vp_splice_nxv2i32_with_firstelt:
511+
; CHECK: # %bb.0:
512+
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
513+
; CHECK-NEXT: vmv.s.x v9, a0
514+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
515+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
516+
; CHECK-NEXT: vmv.v.v v8, v9
517+
; CHECK-NEXT: ret
518+
%va = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0
519+
%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
520+
ret <vscale x 2 x i32> %v
521+
}
522+
523+
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_splat_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
524+
; CHECK-LABEL: test_vp_splice_nxv2i32_with_splat_firstelt:
525+
; CHECK: # %bb.0:
526+
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
527+
; CHECK-NEXT: vmv.v.x v9, a0
528+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
529+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
530+
; CHECK-NEXT: vmv.v.v v8, v9
531+
; CHECK-NEXT: ret
532+
%ins = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0
533+
%splat = shufflevector <vscale x 2 x i32> %ins, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
534+
%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %splat, <vscale x 2 x i32> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
535+
ret <vscale x 2 x i32> %v
536+
}
537+
538+
define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
539+
; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
540+
; CHECK: # %bb.0:
541+
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
542+
; CHECK-NEXT: vfmv.s.f v9, fa0
543+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
544+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
545+
; CHECK-NEXT: vmv.v.v v8, v9
546+
; CHECK-NEXT: ret
547+
%va = insertelement <vscale x 2 x float> poison, float %first, i32 0
548+
%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
549+
ret <vscale x 2 x float> %v
550+
}
551+
552+
define <vscale x 2 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <vscale x 2 x half> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
553+
; ZVFH-LABEL: test_vp_splice_nxv2f16_with_firstelt:
554+
; ZVFH: # %bb.0:
555+
; ZVFH-NEXT: vsetvli a1, zero, e16, m1, ta, ma
556+
; ZVFH-NEXT: vfmv.s.f v9, fa0
557+
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
558+
; ZVFH-NEXT: vslideup.vi v9, v8, 1, v0.t
559+
; ZVFH-NEXT: vmv1r.v v8, v9
560+
; ZVFH-NEXT: ret
561+
;
562+
; ZVFHMIN-LABEL: test_vp_splice_nxv2f16_with_firstelt:
563+
; ZVFHMIN: # %bb.0:
564+
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
565+
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m1, ta, ma
566+
; ZVFHMIN-NEXT: vmv.s.x v9, a1
567+
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
568+
; ZVFHMIN-NEXT: vslideup.vi v9, v8, 1, v0.t
569+
; ZVFHMIN-NEXT: vmv1r.v v8, v9
570+
; ZVFHMIN-NEXT: ret
571+
%va = insertelement <vscale x 2 x half> poison, half %first, i32 0
572+
%v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
573+
ret <vscale x 2 x half> %v
574+
}
575+
576+
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_with_firstelt(bfloat %first, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
577+
; CHECK-LABEL: test_vp_splice_nxv2bf16_with_firstelt:
578+
; CHECK: # %bb.0:
579+
; CHECK-NEXT: fmv.x.h a1, fa0
580+
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
581+
; CHECK-NEXT: vmv.s.x v9, a1
582+
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
583+
; CHECK-NEXT: vslideup.vi v9, v8, 1, v0.t
584+
; CHECK-NEXT: vmv1r.v v8, v9
585+
; CHECK-NEXT: ret
586+
%va = insertelement <vscale x 2 x bfloat> poison, bfloat %first, i32 0
587+
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
588+
ret <vscale x 2 x bfloat> %v
589+
}

0 commit comments

Comments
 (0)