Added RISC-V support information to readme

Author: AnastasiyaChernikova

llvm/tools/llvm-exegesis/README.md

@@ -32,6 +32,8 @@ architectures:
     e.g. pseudo instructions and most register classes are not supported.
 * MIPS
 * PowerPC (PowerPC64LE only)
+* RISCV
+  * Supported extensions: compressed, atomic, multiply-divide, initual vector instructions.
 
 Note that not all benchmarking functionality is guaranteed to work on all platforms.