Skip to content

Commit ae46855

Browse files
[Target] Use getConstantOperand (NFC)
1 parent 1f5934a commit ae46855

File tree

4 files changed

+5
-9
lines changed

4 files changed

+5
-9
lines changed

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7726,8 +7726,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
77267726
}
77277727
}
77287728

7729-
unsigned CPol = cast<ConstantSDNode>(
7730-
Op.getOperand(ArgOffset + Intr->CachePolicyIndex))->getZExtValue();
7729+
unsigned CPol = Op.getConstantOperandVal(ArgOffset + Intr->CachePolicyIndex);
77317730
if (BaseOpcode->Atomic)
77327731
CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization
77337732
if (CPol & ~((IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12) |

llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4068,9 +4068,7 @@ SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
40684068
SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
40694069
SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
40704070
unsigned IntNo =
4071-
cast<ConstantSDNode>(
4072-
Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
4073-
->getZExtValue();
4071+
Op.getConstantOperandVal(Op.getOperand(0).getValueType() == MVT::Other);
40744072
switch (IntNo) {
40754073
default:
40764074
return SDValue(); // Don't custom lower most intrinsics.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11253,9 +11253,9 @@ SDValue PPCTargetLowering::LowerIS_FPCLASS(SDValue Op,
1125311253
SelectionDAG &DAG) const {
1125411254
assert(Subtarget.hasP9Vector() && "Test data class requires Power9");
1125511255
SDValue LHS = Op.getOperand(0);
11256-
const auto *RHS = cast<ConstantSDNode>(Op.getOperand(1));
11256+
uint64_t RHSC = Op.getConstantOperandVal(1);
1125711257
SDLoc Dl(Op);
11258-
FPClassTest Category = static_cast<FPClassTest>(RHS->getZExtValue());
11258+
FPClassTest Category = static_cast<FPClassTest>(RHSC);
1125911259
return getDataClassTest(LHS, Category, Dl, DAG, Subtarget);
1126011260
}
1126111261

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -831,8 +831,7 @@ void RISCVDAGToDAGISel::selectSF_VC_X_SE(SDNode *Node) {
831831
"Unexpected vsetvli intrinsic");
832832

833833
// imm, imm, imm, simm5/scalar, sew, log2lmul, vl
834-
auto *SewSDNode = cast<ConstantSDNode>(Node->getOperand(6));
835-
unsigned Log2SEW = Log2_32(SewSDNode->getZExtValue());
834+
unsigned Log2SEW = Log2_32(Node->getConstantOperandVal(6));
836835
SDValue SEWOp =
837836
CurDAG->getTargetConstant(Log2SEW, DL, Subtarget->getXLenVT());
838837
SmallVector<SDValue, 8> Operands = {Node->getOperand(2), Node->getOperand(3),

0 commit comments

Comments
 (0)