[RISCV] Add build vector coverage for rva22u + V

Author: preames

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

@@ -1,7 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+rva22u64 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVA22U64
 
 ; Tests that a floating-point build_vector doesn't try and generate a VID
 ; instruction
@@ -206,19 +207,47 @@ define <8 x float> @splat_idx_v8f32(<8 x float> %v, i64 %idx) {
 
 ; Test that we pull the vlse of the constant pool out of the loop.
 define dso_local void @splat_load_licm(ptr %0) {
-; CHECK-LABEL: splat_load_licm:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a1, 1
-; CHECK-NEXT:    add a1, a0, a1
-; CHECK-NEXT:    lui a2, 263168
-; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT:    vmv.v.x v8, a2
-; CHECK-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vse32.v v8, (a0)
-; CHECK-NEXT:    addi a0, a0, 16
-; CHECK-NEXT:    bne a0, a1, .LBB12_1
-; CHECK-NEXT:  # %bb.2:
-; CHECK-NEXT:    ret
+; RV32-LABEL: splat_load_licm:
+; RV32:       # %bb.0:
+; RV32-NEXT:    lui a1, 1
+; RV32-NEXT:    add a1, a0, a1
+; RV32-NEXT:    lui a2, 263168
+; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT:    vmv.v.x v8, a2
+; RV32-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV32-NEXT:    vse32.v v8, (a0)
+; RV32-NEXT:    addi a0, a0, 16
+; RV32-NEXT:    bne a0, a1, .LBB12_1
+; RV32-NEXT:  # %bb.2:
+; RV32-NEXT:    ret
+;
+; RV64V-LABEL: splat_load_licm:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    lui a1, 1
+; RV64V-NEXT:    add a1, a0, a1
+; RV64V-NEXT:    lui a2, 263168
+; RV64V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RV64V-NEXT:    vmv.v.x v8, a2
+; RV64V-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RV64V-NEXT:    vse32.v v8, (a0)
+; RV64V-NEXT:    addi a0, a0, 16
+; RV64V-NEXT:    bne a0, a1, .LBB12_1
+; RV64V-NEXT:  # %bb.2:
+; RV64V-NEXT:    ret
+;
+; RVA22U64-LABEL: splat_load_licm:
+; RVA22U64:       # %bb.0:
+; RVA22U64-NEXT:    lui a1, 1
+; RVA22U64-NEXT:    add a1, a1, a0
+; RVA22U64-NEXT:    lui a2, 263168
+; RVA22U64-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; RVA22U64-NEXT:    vmv.v.x v8, a2
+; RVA22U64-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
+; RVA22U64-NEXT:    vse32.v v8, (a0)
+; RVA22U64-NEXT:    addi a0, a0, 16
+; RVA22U64-NEXT:    bne a0, a1, .LBB12_1
+; RVA22U64-NEXT:  # %bb.2:
+; RVA22U64-NEXT:    ret
   br label %2
 
 2:                                                ; preds = %2, %1