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[RISCV] Update to Xqciint v0.4 (#130219)
The Xqci 0.7.0 spec just came out, with some updates to Xqciint, bringing it to v0.4. The main update of any relevance is that `qc.c.mienter` and `qc.c.mienter.nest` now update both the stack pointer and the frame pointer (before, they only updated the stack pointer). They both remain compatible with the frame pointer convention. This change bumps the Xqciint version, and ensures that we don't emit the unneeded frame pointer adjustment instruction after `qc.c.mienter(.nest)`.
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‎clang/include/clang/Basic/AttrDocs.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2883,7 +2883,7 @@ https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Function-Attributes.html
28832883
https://riscv.org/specifications/privileged-isa/
28842884
The RISC-V Instruction Set Manual Volume II: Privileged Architecture
28852885
Version 1.10.
2886-
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.6
2886+
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.7
28872887
}];
28882888
}
28892889

‎clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@
201201
// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension)
202202
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
203203
// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
204-
// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
204+
// CHECK-NEXT: xqciint 0.4 'Xqciint' (Qualcomm uC Interrupts Extension)
205205
// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
206206
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
207207
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -454,7 +454,7 @@ The current vendor extensions supported are:
454454
LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
455455

456456
``experimental-Xqciint``
457-
LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
457+
LLVM implements `version 0.4 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
458458

459459
``experimental-Xqcilia``
460460
LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1351,7 +1351,7 @@ def HasVendorXqcicm
13511351
"'Xqcicm' (Qualcomm uC Conditional Move Extension)">;
13521352

13531353
def FeatureVendorXqciint
1354-
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Interrupts Extension",
1354+
: RISCVExperimentalExtension<0, 4, "Qualcomm uC Interrupts Extension",
13551355
[FeatureStdExtZca]>;
13561356
def HasVendorXqciint
13571357
: Predicate<"Subtarget->hasVendorXqciint()">,

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1008,10 +1008,9 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
10081008
// The frame pointer does need to be reserved from register allocation.
10091009
assert(MF.getRegInfo().isReserved(FPReg) && "FP not reserved");
10101010

1011-
// Xqccmp with hasFP will update FP using `qc.cm.pushfp`, so we don't need
1012-
// to update it again, but we do need to emit the `.cfi_def_cfa` below.
1013-
if (RVFI->getPushPopKind(MF) !=
1014-
RISCVMachineFunctionInfo::PushPopKind::VendorXqccmp) {
1011+
// Some stack management variants automatically keep FP updated, so we don't
1012+
// need an instruction to do so.
1013+
if (!RVFI->hasImplicitFPUpdates(MF)) {
10151014
RI->adjustReg(
10161015
MBB, MBBI, DL, FPReg, SPReg,
10171016
StackOffset::getFixed(RealStackSize - RVFI->getVarArgsSaveSize()),

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -568,7 +568,7 @@ let Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1 in {
568568

569569
let mayLoad = 0, mayStore = 1,
570570
Uses = [X1, X2, X5, X6, X7, X8, X10, X11, X12, X13, X14, X15, X16, X17, X28, X29, X30, X31],
571-
Defs = [X2] in {
571+
Defs = [X2, X8] in {
572572
def QC_C_MIENTER : QCIRVInst16CI_NONE<0b10000, "qc.c.mienter">;
573573
def QC_C_MIENTER_NEST : QCIRVInst16CI_NONE<0b10001, "qc.c.mienter.nest">;
574574
} // mayLoad = 1, mayStore = 1, Uses = [...], Defs = [...]

‎llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.cpp

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,29 @@ RISCVMachineFunctionInfo::getPushPopKind(const MachineFunction &MF) const {
100100
return PushPopKind::None;
101101
}
102102

103+
bool RISCVMachineFunctionInfo::hasImplicitFPUpdates(
104+
const MachineFunction &MF) const {
105+
switch (getInterruptStackKind(MF)) {
106+
case InterruptStackKind::QCINest:
107+
case InterruptStackKind::QCINoNest:
108+
// QC.C.MIENTER and QC.C.MIENTER.NEST both update FP on function entry.
109+
return true;
110+
default:
111+
break;
112+
}
113+
114+
switch (getPushPopKind(MF)) {
115+
case PushPopKind::VendorXqccmp:
116+
// When using Xqccmp, we will use `QC.CM.PUSHFP` when Frame Pointers are
117+
// enabled, which will update FP.
118+
return true;
119+
default:
120+
break;
121+
}
122+
123+
return false;
124+
}
125+
103126
void RISCVMachineFunctionInfo::initializeBaseYamlFields(
104127
const yaml::RISCVMachineFunctionInfo &YamlMFI) {
105128
VarArgsFrameIndex = YamlMFI.VarArgsFrameIndex;

‎llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -166,6 +166,12 @@ class RISCVMachineFunctionInfo : public MachineFunctionInfo {
166166
unsigned getQCIInterruptStackSize() const { return QCIInterruptStackSize; }
167167
void setQCIInterruptStackSize(unsigned Size) { QCIInterruptStackSize = Size; }
168168

169+
// Some Stack Management Variants automatically update FP in a frame-pointer
170+
// convention compatible way - which means we don't need to manually update
171+
// the FP, but we still need to emit the correct CFI information for
172+
// calculating the CFA based on FP.
173+
bool hasImplicitFPUpdates(const MachineFunction &MF) const;
174+
169175
void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI);
170176

171177
void addSExt32Register(Register Reg);

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -411,7 +411,7 @@
411411
; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2"
412412
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
413413
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
414-
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p2"
414+
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p4"
415415
; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
416416
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
417417
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"

‎llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,6 @@ define void @test_nest_empty() "interrupt"="qci-nest" {
6565
; QCI-FP-NEXT: .cfi_offset t4, -72
6666
; QCI-FP-NEXT: .cfi_offset t5, -76
6767
; QCI-FP-NEXT: .cfi_offset t6, -80
68-
; QCI-FP-NEXT: addi s0, sp, 96
6968
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
7069
; QCI-FP-NEXT: .cfi_def_cfa sp, 96
7170
; QCI-FP-NEXT: qc.c.mileaveret
@@ -140,7 +139,6 @@ define void @test_nonest_empty() "interrupt"="qci-nonest" {
140139
; QCI-FP-NEXT: .cfi_offset t4, -72
141140
; QCI-FP-NEXT: .cfi_offset t5, -76
142141
; QCI-FP-NEXT: .cfi_offset t6, -80
143-
; QCI-FP-NEXT: addi s0, sp, 96
144142
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
145143
; QCI-FP-NEXT: .cfi_def_cfa sp, 96
146144
; QCI-FP-NEXT: qc.c.mileaveret
@@ -223,7 +221,6 @@ define void @test_nest_asm() "interrupt"="qci-nest" {
223221
; QCI-FP-NEXT: .cfi_offset t4, -72
224222
; QCI-FP-NEXT: .cfi_offset t5, -76
225223
; QCI-FP-NEXT: .cfi_offset t6, -80
226-
; QCI-FP-NEXT: addi s0, sp, 96
227224
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
228225
; QCI-FP-NEXT: li a0, 1
229226
; QCI-FP-NEXT: #APP
@@ -315,7 +312,6 @@ define void @test_nonest_asm() "interrupt"="qci-nonest" {
315312
; QCI-FP-NEXT: .cfi_offset t4, -72
316313
; QCI-FP-NEXT: .cfi_offset t5, -76
317314
; QCI-FP-NEXT: .cfi_offset t6, -80
318-
; QCI-FP-NEXT: addi s0, sp, 96
319315
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
320316
; QCI-FP-NEXT: li a0, 1
321317
; QCI-FP-NEXT: #APP
@@ -423,7 +419,6 @@ define void @test_nest_call() "interrupt"="qci-nest" {
423419
; QCI-FP-NEXT: .cfi_offset t6, -80
424420
; QCI-FP-NEXT: addi sp, sp, -16
425421
; QCI-FP-NEXT: .cfi_def_cfa_offset 112
426-
; QCI-FP-NEXT: addi s0, sp, 112
427422
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
428423
; QCI-FP-NEXT: li a0, 4
429424
; QCI-FP-NEXT: li a2, 1
@@ -548,7 +543,6 @@ define void @test_nonest_call() "interrupt"="qci-nonest" {
548543
; QCI-FP-NEXT: .cfi_offset t6, -80
549544
; QCI-FP-NEXT: addi sp, sp, -16
550545
; QCI-FP-NEXT: .cfi_def_cfa_offset 112
551-
; QCI-FP-NEXT: addi s0, sp, 112
552546
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
553547
; QCI-FP-NEXT: li a0, 4
554548
; QCI-FP-NEXT: li a2, 1
@@ -807,7 +801,6 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
807801
; QCI-FP-NEXT: .cfi_offset s9, -132
808802
; QCI-FP-NEXT: .cfi_offset s10, -136
809803
; QCI-FP-NEXT: .cfi_offset s11, -140
810-
; QCI-FP-NEXT: addi s0, sp, 176
811804
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
812805
; QCI-FP-NEXT: lui t1, %hi(var)
813806
; QCI-FP-NEXT: lw a0, %lo(var)(t1)
@@ -1264,7 +1257,6 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
12641257
; QCI-FP-NEXT: .cfi_offset s9, -132
12651258
; QCI-FP-NEXT: .cfi_offset s10, -136
12661259
; QCI-FP-NEXT: .cfi_offset s11, -140
1267-
; QCI-FP-NEXT: addi s0, sp, 176
12681260
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
12691261
; QCI-FP-NEXT: lui t1, %hi(var)
12701262
; QCI-FP-NEXT: lw a0, %lo(var)(t1)
@@ -1765,7 +1757,6 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
17651757
; QCI-FP-NEXT: .cfi_offset s9, -132
17661758
; QCI-FP-NEXT: .cfi_offset s10, -136
17671759
; QCI-FP-NEXT: .cfi_offset s11, -140
1768-
; QCI-FP-NEXT: addi s0, sp, 240
17691760
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
17701761
; QCI-FP-NEXT: lui s6, %hi(var)
17711762
; QCI-FP-NEXT: lw a0, %lo(var)(s6)
@@ -2356,7 +2347,6 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
23562347
; QCI-FP-NEXT: .cfi_offset s9, -132
23572348
; QCI-FP-NEXT: .cfi_offset s10, -136
23582349
; QCI-FP-NEXT: .cfi_offset s11, -140
2359-
; QCI-FP-NEXT: addi s0, sp, 240
23602350
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
23612351
; QCI-FP-NEXT: lui s6, %hi(var)
23622352
; QCI-FP-NEXT: lw a0, %lo(var)(s6)
@@ -2768,7 +2758,6 @@ define void @test_nest_explicit_s11() "interrupt"="qci-nest" {
27682758
; QCI-FP-NEXT: .cfi_def_cfa_offset 112
27692759
; QCI-FP-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
27702760
; QCI-FP-NEXT: .cfi_offset s11, -100
2771-
; QCI-FP-NEXT: addi s0, sp, 112
27722761
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
27732762
; QCI-FP-NEXT: #APP
27742763
; QCI-FP-NEXT: li s4, 0
@@ -2877,7 +2866,6 @@ define void @test_nonest_explicit_s11() "interrupt"="qci-nonest" {
28772866
; QCI-FP-NEXT: .cfi_def_cfa_offset 112
28782867
; QCI-FP-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
28792868
; QCI-FP-NEXT: .cfi_offset s11, -100
2880-
; QCI-FP-NEXT: addi s0, sp, 112
28812869
; QCI-FP-NEXT: .cfi_def_cfa s0, 0
28822870
; QCI-FP-NEXT: #APP
28832871
; QCI-FP-NEXT: li s11, 0

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -656,7 +656,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
656656
for (StringRef Input :
657657
{"rv64i_xqcisls0p2", "rv64i_xqcia0p4", "rv64i_xqciac0p3",
658658
"rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2",
659-
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2",
659+
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p4",
660660
"rv64i_xqcilo0p2", "rv64i_xqcilia0p2", "rv64i_xqcibm0p4"}) {
661661
EXPECT_THAT(
662662
toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
@@ -1132,7 +1132,7 @@ Experimental extensions
11321132
xqcicm 0.2
11331133
xqcics 0.2
11341134
xqcicsr 0.2
1135-
xqciint 0.2
1135+
xqciint 0.4
11361136
xqcilia 0.2
11371137
xqcilo 0.2
11381138
xqcilsm 0.2

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