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[RISCV] Split PseudoVFWADD, PseudoVFWSUB, and PseudoVFWMUL by SEW
Co-authored-by: Wang Pengcheng <[email protected]>
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7 files changed

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‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 40 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3038,14 +3038,13 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
30383038
#define CASE_WIDEOP_OPCODE_LMULS(OP) \
30393039
CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \
30403040
case CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
3041-
// clang-format on
30423041

30433042
#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL) \
30443043
case RISCV::PseudoV##OP##_##LMUL##_TIED: \
30453044
NewOpc = RISCV::PseudoV##OP##_##LMUL; \
30463045
break;
30473046

3048-
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) \
3047+
#define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) \
30493048
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \
30503049
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \
30513050
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \
@@ -3056,15 +3055,50 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
30563055
CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \
30573056
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
30583057

3058+
// FP Widening Ops may by SEW aware. Create SEW aware cases for these cases.
3059+
#define CASE_FP_WIDEOP_OPCODE_COMMON(OP, LMUL, SEW) \
3060+
RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED
3061+
3062+
#define CASE_FP_WIDEOP_OPCODE_LMULS_MF4(OP) \
3063+
CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF4, E16): \
3064+
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E16): \
3065+
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E32): \
3066+
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E16): \
3067+
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E32): \
3068+
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E16): \
3069+
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E32): \
3070+
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E16): \
3071+
case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E32) \
3072+
3073+
#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL, SEW) \
3074+
case RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED: \
3075+
NewOpc = RISCV::PseudoV##OP##_##LMUL##_##SEW; \
3076+
break;
3077+
3078+
#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP) \
3079+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16) \
3080+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16) \
3081+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E32) \
3082+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16) \
3083+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E32) \
3084+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16) \
3085+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E32) \
3086+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16) \
3087+
CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E32) \
3088+
3089+
#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS(OP) \
3090+
CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
3091+
// clang-format on
3092+
30593093
MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
30603094
LiveVariables *LV,
30613095
LiveIntervals *LIS) const {
30623096
MachineInstrBuilder MIB;
30633097
switch (MI.getOpcode()) {
30643098
default:
30653099
return nullptr;
3066-
case CASE_WIDEOP_OPCODE_LMULS_MF4(FWADD_WV):
3067-
case CASE_WIDEOP_OPCODE_LMULS_MF4(FWSUB_WV): {
3100+
case CASE_FP_WIDEOP_OPCODE_LMULS_MF4(FWADD_WV):
3101+
case CASE_FP_WIDEOP_OPCODE_LMULS_MF4(FWSUB_WV): {
30683102
assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
30693103
MI.getNumExplicitOperands() == 7 &&
30703104
"Expect 7 explicit operands rd, rs2, rs1, rm, vl, sew, policy");
@@ -3077,8 +3111,8 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
30773111
switch (MI.getOpcode()) {
30783112
default:
30793113
llvm_unreachable("Unexpected opcode");
3080-
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(FWADD_WV)
3081-
CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(FWSUB_WV)
3114+
CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4(FWADD_WV)
3115+
CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_MF4(FWSUB_WV)
30823116
}
30833117
// clang-format on
30843118

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 71 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -2213,11 +2213,13 @@ multiclass VPseudoTiedBinaryRoundingMode<VReg RetClass,
22132213
DAGOperand Op2Class,
22142214
LMULInfo MInfo,
22152215
string Constraint = "",
2216+
int sew = 0,
22162217
int TargetConstraintType = 1> {
2218+
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
22172219
let VLMul = MInfo.value in {
2218-
def "_" # MInfo.MX # "_TIED":
2220+
def suffix # "_TIED":
22192221
VPseudoTiedBinaryNoMaskRoundingMode<RetClass, Op2Class, Constraint, TargetConstraintType>;
2220-
def "_" # MInfo.MX # "_MASK_TIED" :
2222+
def suffix # "_MASK_TIED" :
22212223
VPseudoTiedBinaryMaskRoundingMode<RetClass, Op2Class, Constraint, TargetConstraintType>,
22222224
RISCVMaskedPseudo<MaskIdx=2>;
22232225
}
@@ -2334,9 +2336,9 @@ multiclass VPseudoBinaryW_VV<LMULInfo m> {
23342336
"@earlyclobber $rd", TargetConstraintType=3>;
23352337
}
23362338

2337-
multiclass VPseudoBinaryW_VV_RM<LMULInfo m> {
2339+
multiclass VPseudoBinaryW_VV_RM<LMULInfo m, int sew = 0> {
23382340
defm _VV : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
2339-
"@earlyclobber $rd", UsesVXRM=0,
2341+
"@earlyclobber $rd", sew, UsesVXRM=0,
23402342
TargetConstraintType=3>;
23412343
}
23422344

@@ -2356,10 +2358,10 @@ multiclass VPseudoBinaryW_VF<LMULInfo m, FPR_Info f> {
23562358
"@earlyclobber $rd">;
23572359
}
23582360

2359-
multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f> {
2361+
multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f, int sew = 0> {
23602362
defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass,
23612363
f.fprclass, m,
2362-
"@earlyclobber $rd",
2364+
"@earlyclobber $rd", sew,
23632365
UsesVXRM=0,
23642366
TargetConstraintType=3>;
23652367
}
@@ -2371,11 +2373,13 @@ multiclass VPseudoBinaryW_WV<LMULInfo m> {
23712373
"@earlyclobber $rd", TargetConstraintType=3>;
23722374
}
23732375

2374-
multiclass VPseudoBinaryW_WV_RM<LMULInfo m> {
2376+
multiclass VPseudoBinaryW_WV_RM<LMULInfo m, int sew = 0> {
23752377
defm _WV : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass, m.vrclass, m,
2376-
"@earlyclobber $rd", UsesVXRM=0, TargetConstraintType=3>;
2378+
"@earlyclobber $rd", sew, UsesVXRM = 0,
2379+
TargetConstraintType = 3>;
23772380
defm _WV : VPseudoTiedBinaryRoundingMode<m.wvrclass, m.vrclass, m,
2378-
"@earlyclobber $rd", TargetConstraintType=3>;
2381+
"@earlyclobber $rd", sew,
2382+
TargetConstraintType = 3>;
23792383
}
23802384

23812385
multiclass VPseudoBinaryW_WX<LMULInfo m> {
@@ -2387,11 +2391,11 @@ multiclass VPseudoBinaryW_WF<LMULInfo m, FPR_Info f, int TargetConstraintType =
23872391
f.fprclass, m, /*Constraint*/ "", TargetConstraintType=TargetConstraintType>;
23882392
}
23892393

2390-
multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f> {
2394+
multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f, int sew = 0> {
23912395
defm "_W" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass,
23922396
f.fprclass, m,
23932397
Constraint="",
2394-
sew=0,
2398+
sew=sew,
23952399
UsesVXRM=0,
23962400
TargetConstraintType=3>;
23972401
}
@@ -2979,16 +2983,17 @@ multiclass VPseudoVWMUL_VV_VX {
29792983

29802984
multiclass VPseudoVWMUL_VV_VF_RM {
29812985
foreach m = MxListFW in {
2982-
defm "" : VPseudoBinaryW_VV_RM<m>,
2986+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
2987+
defm "" : VPseudoBinaryW_VV_RM<m, sew=e>,
29832988
SchedBinary<"WriteVFWMulV", "ReadVFWMulV", "ReadVFWMulV", m.MX,
2984-
forceMergeOpRead=true>;
2989+
e, forceMergeOpRead=true>;
29852990
}
29862991

29872992
foreach f = FPListW in {
29882993
foreach m = f.MxListFW in {
2989-
defm "" : VPseudoBinaryW_VF_RM<m, f>,
2994+
defm "" : VPseudoBinaryW_VF_RM<m, f, sew=f.SEW>,
29902995
SchedBinary<"WriteVFWMulF", "ReadVFWMulV", "ReadVFWMulF", m.MX,
2991-
forceMergeOpRead=true>;
2996+
f.SEW, forceMergeOpRead=true>;
29922997
}
29932998
}
29942999
}
@@ -3007,31 +3012,33 @@ multiclass VPseudoVWALU_WV_WX {
30073012

30083013
multiclass VPseudoVFWALU_VV_VF_RM {
30093014
foreach m = MxListFW in {
3010-
defm "" : VPseudoBinaryW_VV_RM<m>,
3011-
SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,
3012-
forceMergeOpRead=true>;
3015+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3016+
defm "" : VPseudoBinaryW_VV_RM<m, sew=e>,
3017+
SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,
3018+
e, forceMergeOpRead=true>;
30133019
}
30143020

30153021
foreach f = FPListW in {
30163022
foreach m = f.MxListFW in {
3017-
defm "" : VPseudoBinaryW_VF_RM<m, f>,
3023+
defm "" : VPseudoBinaryW_VF_RM<m, f, sew=f.SEW>,
30183024
SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,
3019-
forceMergeOpRead=true>;
3025+
f.SEW, forceMergeOpRead=true>;
30203026
}
30213027
}
30223028
}
30233029

30243030
multiclass VPseudoVFWALU_WV_WF_RM {
30253031
foreach m = MxListFW in {
3026-
defm "" : VPseudoBinaryW_WV_RM<m>,
3027-
SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,
3028-
forceMergeOpRead=true>;
3032+
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3033+
defm "" : VPseudoBinaryW_WV_RM<m, sew=e>,
3034+
SchedBinary<"WriteVFWALUV", "ReadVFWALUV", "ReadVFWALUV", m.MX,
3035+
e, forceMergeOpRead=true>;
30293036
}
30303037
foreach f = FPListW in {
30313038
foreach m = f.MxListFW in {
3032-
defm "" : VPseudoBinaryW_WF_RM<m, f>,
3039+
defm "" : VPseudoBinaryW_WF_RM<m, f, sew=f.SEW>,
30333040
SchedBinary<"WriteVFWALUF", "ReadVFWALUV", "ReadVFWALUF", m.MX,
3034-
forceMergeOpRead=true>;
3041+
f.SEW, forceMergeOpRead=true>;
30353042
}
30363043
}
30373044
}
@@ -5028,13 +5035,16 @@ multiclass VPatBinaryW_VV<string intrinsic, string instruction,
50285035
}
50295036

50305037
multiclass VPatBinaryW_VV_RM<string intrinsic, string instruction,
5031-
list<VTypeInfoToWide> vtilist> {
5038+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {
50325039
foreach VtiToWti = vtilist in {
50335040
defvar Vti = VtiToWti.Vti;
50345041
defvar Wti = VtiToWti.Wti;
5042+
defvar name = !if(isSEWAware,
5043+
instruction # "_VV_" # Vti.LMul.MX # "_E" # Vti.SEW,
5044+
instruction # "_VV_" # Vti.LMul.MX);
50355045
let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,
50365046
GetVTypePredicates<Wti>.Predicates) in
5037-
defm : VPatBinaryRoundingMode<intrinsic, instruction # "_VV_" # Vti.LMul.MX,
5047+
defm : VPatBinaryRoundingMode<intrinsic, name,
50385048
Wti.Vector, Vti.Vector, Vti.Vector, Vti.Mask,
50395049
Vti.Log2SEW, Wti.RegClass,
50405050
Vti.RegClass, Vti.RegClass>;
@@ -5057,14 +5067,17 @@ multiclass VPatBinaryW_VX<string intrinsic, string instruction,
50575067
}
50585068

50595069
multiclass VPatBinaryW_VX_RM<string intrinsic, string instruction,
5060-
list<VTypeInfoToWide> vtilist> {
5070+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {
50615071
foreach VtiToWti = vtilist in {
50625072
defvar Vti = VtiToWti.Vti;
50635073
defvar Wti = VtiToWti.Wti;
50645074
defvar kind = "V"#Vti.ScalarSuffix;
5075+
defvar name = !if(isSEWAware,
5076+
instruction#"_"#kind#"_"#Vti.LMul.MX # "_E" # Vti.SEW,
5077+
instruction#"_"#kind#"_"#Vti.LMul.MX);
50655078
let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,
50665079
GetVTypePredicates<Wti>.Predicates) in
5067-
defm : VPatBinaryRoundingMode<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
5080+
defm : VPatBinaryRoundingMode<intrinsic, name,
50685081
Wti.Vector, Vti.Vector, Vti.Scalar, Vti.Mask,
50695082
Vti.Log2SEW, Wti.RegClass,
50705083
Vti.RegClass, Vti.ScalarRegClass>;
@@ -5101,27 +5114,30 @@ multiclass VPatBinaryW_WV<string intrinsic, string instruction,
51015114
}
51025115

51035116
multiclass VPatBinaryW_WV_RM<string intrinsic, string instruction,
5104-
list<VTypeInfoToWide> vtilist> {
5117+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {
51055118
foreach VtiToWti = vtilist in {
51065119
defvar Vti = VtiToWti.Vti;
51075120
defvar Wti = VtiToWti.Wti;
5121+
defvar name = !if(isSEWAware,
5122+
instruction # "_WV_" # Vti.LMul.MX # "_E" # Vti.SEW,
5123+
instruction # "_WV_" # Vti.LMul.MX);
51085124
let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,
51095125
GetVTypePredicates<Wti>.Predicates) in {
5110-
def : VPatTiedBinaryNoMaskRoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5126+
def : VPatTiedBinaryNoMaskRoundingMode<intrinsic, name,
51115127
Wti.Vector, Vti.Vector,
51125128
Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;
5113-
def : VPatBinaryNoMaskTURoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5129+
def : VPatBinaryNoMaskTURoundingMode<intrinsic, name,
51145130
Wti.Vector, Wti.Vector, Vti.Vector, Vti.Log2SEW,
51155131
Wti.RegClass, Wti.RegClass, Vti.RegClass>;
51165132
let AddedComplexity = 1 in {
5117-
def : VPatTiedBinaryNoMaskTURoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5133+
def : VPatTiedBinaryNoMaskTURoundingMode<intrinsic, name,
51185134
Wti.Vector, Vti.Vector,
51195135
Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;
5120-
def : VPatTiedBinaryMaskRoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5136+
def : VPatTiedBinaryMaskRoundingMode<intrinsic, name,
51215137
Wti.Vector, Vti.Vector, Vti.Mask,
51225138
Vti.Log2SEW, Wti.RegClass, Vti.RegClass>;
51235139
}
5124-
def : VPatBinaryMaskTARoundingMode<intrinsic, instruction # "_WV_" # Vti.LMul.MX,
5140+
def : VPatBinaryMaskTARoundingMode<intrinsic, name,
51255141
Wti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
51265142
Vti.Log2SEW, Wti.RegClass,
51275143
Wti.RegClass, Vti.RegClass>;
@@ -5145,14 +5161,17 @@ multiclass VPatBinaryW_WX<string intrinsic, string instruction,
51455161
}
51465162

51475163
multiclass VPatBinaryW_WX_RM<string intrinsic, string instruction,
5148-
list<VTypeInfoToWide> vtilist> {
5164+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 0> {
51495165
foreach VtiToWti = vtilist in {
51505166
defvar Vti = VtiToWti.Vti;
51515167
defvar Wti = VtiToWti.Wti;
51525168
defvar kind = "W"#Vti.ScalarSuffix;
5169+
defvar name = !if(isSEWAware,
5170+
instruction#"_"#kind#"_"#Vti.LMul.MX#"_E"#Vti.SEW,
5171+
instruction#"_"#kind#"_"#Vti.LMul.MX);
51535172
let Predicates = !listconcat(GetVTypePredicates<Vti>.Predicates,
51545173
GetVTypePredicates<Wti>.Predicates) in
5155-
defm : VPatBinaryRoundingMode<intrinsic, instruction#"_"#kind#"_"#Vti.LMul.MX,
5174+
defm : VPatBinaryRoundingMode<intrinsic, name,
51565175
Wti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
51575176
Vti.Log2SEW, Wti.RegClass,
51585177
Wti.RegClass, Vti.ScalarRegClass>;
@@ -5417,20 +5436,22 @@ multiclass VPatBinaryW_VV_VX<string intrinsic, string instruction,
54175436
: VPatBinaryW_VV<intrinsic, instruction, vtilist>,
54185437
VPatBinaryW_VX<intrinsic, instruction, vtilist>;
54195438

5420-
multiclass VPatBinaryW_VV_VX_RM<string intrinsic, string instruction,
5421-
list<VTypeInfoToWide> vtilist>
5422-
: VPatBinaryW_VV_RM<intrinsic, instruction, vtilist>,
5423-
VPatBinaryW_VX_RM<intrinsic, instruction, vtilist>;
5439+
multiclass
5440+
VPatBinaryW_VV_VX_RM<string intrinsic, string instruction,
5441+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 0>
5442+
: VPatBinaryW_VV_RM<intrinsic, instruction, vtilist, isSEWAware>,
5443+
VPatBinaryW_VX_RM<intrinsic, instruction, vtilist, isSEWAware>;
54245444

54255445
multiclass VPatBinaryW_WV_WX<string intrinsic, string instruction,
54265446
list<VTypeInfoToWide> vtilist>
54275447
: VPatBinaryW_WV<intrinsic, instruction, vtilist>,
54285448
VPatBinaryW_WX<intrinsic, instruction, vtilist>;
54295449

5430-
multiclass VPatBinaryW_WV_WX_RM<string intrinsic, string instruction,
5431-
list<VTypeInfoToWide> vtilist>
5432-
: VPatBinaryW_WV_RM<intrinsic, instruction, vtilist>,
5433-
VPatBinaryW_WX_RM<intrinsic, instruction, vtilist>;
5450+
multiclass
5451+
VPatBinaryW_WV_WX_RM<string intrinsic, string instruction,
5452+
list<VTypeInfoToWide> vtilist, bit isSEWAware = 0>
5453+
: VPatBinaryW_WV_RM<intrinsic, instruction, vtilist, isSEWAware>,
5454+
VPatBinaryW_WX_RM<intrinsic, instruction, vtilist, isSEWAware>;
54345455

54355456
multiclass VPatBinaryV_WV_WX_WI<string intrinsic, string instruction,
54365457
list<VTypeInfoToWide> vtilist>
@@ -7073,13 +7094,13 @@ defm : VPatBinaryV_VX_RM<"int_riscv_vfrsub", "PseudoVFRSUB", AllFloatVectors,
70737094
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
70747095
//===----------------------------------------------------------------------===//
70757096
defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwadd", "PseudoVFWADD",
7076-
AllWidenableFloatVectors>;
7097+
AllWidenableFloatVectors, isSEWAware=1>;
70777098
defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwsub", "PseudoVFWSUB",
7078-
AllWidenableFloatVectors>;
7099+
AllWidenableFloatVectors, isSEWAware=1>;
70797100
defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwadd_w", "PseudoVFWADD",
7080-
AllWidenableFloatVectors>;
7101+
AllWidenableFloatVectors, isSEWAware=1>;
70817102
defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwsub_w", "PseudoVFWSUB",
7082-
AllWidenableFloatVectors>;
7103+
AllWidenableFloatVectors, isSEWAware=1>;
70837104

70847105
//===----------------------------------------------------------------------===//
70857106
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
@@ -7095,7 +7116,7 @@ defm : VPatBinaryV_VX_RM<"int_riscv_vfrdiv", "PseudoVFRDIV",
70957116
// 13.5. Vector Widening Floating-Point Multiply
70967117
//===----------------------------------------------------------------------===//
70977118
defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwmul", "PseudoVFWMUL",
7098-
AllWidenableFloatVectors>;
7119+
AllWidenableFloatVectors, isSEWAware=1>;
70997120

71007121
//===----------------------------------------------------------------------===//
71017122
// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions

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