Skip to content

Commit aede380

Browse files
sunshaocesunshaoce
authored
[RISCV] Add processor definition for SpacemiT-X60 (#94564)
SpacemiT-X60 is an RVV 1.0 core integrated into the SpacemiT-K1, an 8-core SoC, and it is incorporated into the BPi-F3 development board. According to the [document](https://developer.spacemit.com/#/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb), relevant information for extensions has been obtained. BPi-F3 Datasheet: https://docs.banana-pi.org/en/BPI-F3/SpacemiT_K1_datasheet Spacemit-K1 Datasheet: https://developer.spacemit.com/#/documentation?token=DBd4wvqoqi2fiqkiERTcbEDknBh
1 parent f1eae81 commit aede380

File tree

3 files changed

+74
-2
lines changed

3 files changed

+74
-2
lines changed

‎clang/test/Driver/riscv-cpus.c

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,62 @@
3131
// MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
3232
// MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
3333

34+
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
35+
// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
36+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m"
37+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+a"
38+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+f"
39+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+d"
40+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c"
41+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+v"
42+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zic64b"
43+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbom"
44+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbop"
45+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicboz"
46+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccamoa"
47+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccif"
48+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicclsm"
49+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse"
50+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicntr"
51+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicond"
52+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicsr"
53+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zifencei"
54+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihintpause"
55+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihpm"
56+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+za64rs"
57+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfh"
58+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfhmin"
59+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zba"
60+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbb"
61+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbc"
62+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbkc"
63+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs"
64+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zkt"
65+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32f"
66+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x"
67+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64d"
68+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64f"
69+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x"
70+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfh"
71+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvfhmin"
72+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvkt"
73+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b"
74+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl256b"
75+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl32b"
76+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b"
77+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ssccptr"
78+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscofpmf"
79+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sscounterenw"
80+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstc"
81+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala"
82+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvecd"
83+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svade"
84+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare"
85+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval"
86+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot"
87+
// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
88+
// MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
89+
3490
// We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
3591
// RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
3692
// RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s

‎clang/test/Misc/target-invalid-cpu-note.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -85,12 +85,12 @@
8585

8686
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
8787
// RISCV64: error: unknown target CPU 'not-a-cpu'
88-
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
88+
// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu{{$}}
8989

9090
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
9191
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
9292
// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
9393

9494
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
9595
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
96-
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
96+
// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -381,3 +381,19 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
381381
TuneZExtHFusion,
382382
TuneZExtWFusion,
383383
TuneShiftedZExtWFusion]>;
384+
385+
def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
386+
NoSchedModel,
387+
!listconcat(RVA22S64Features,
388+
[FeatureStdExtV,
389+
FeatureStdExtSscofpmf,
390+
FeatureStdExtSstc,
391+
FeatureStdExtSvnapot,
392+
FeatureStdExtZbc,
393+
FeatureStdExtZbkc,
394+
FeatureStdExtZfh,
395+
FeatureStdExtZicond,
396+
FeatureStdExtZvfh,
397+
FeatureStdExtZvkt,
398+
FeatureStdExtZvl256b]),
399+
[TuneDLenFactor2]>;

0 commit comments

Comments
 (0)