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[RISCV] Assembler support for XRivosVizip (#127694)
This implements assembler support for the XRivosVizip custom/vendor extension from Rivos Inc. which is defined in: https://github.com/rivosinc/rivos-custom-extensions (See src/xrivosvizip.adoc) Codegen support will follow in a separate change.
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‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -203,6 +203,7 @@
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// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
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// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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// CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips)
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// CHECK-EMPTY:
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// CHECK-NEXT: Supported Profiles
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// CHECK-NEXT: rva20s64

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

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@@ -711,6 +711,9 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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"Qualcomm uC Conditional Move");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqciint, DecoderTableXqciint32,
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"Qualcomm uC Interrupts");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXRivosVizip, DecoderTableXRivos32,
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"Rivos");
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TRY_TO_DECODE(true, DecoderTable32, "RISCV32");
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return MCDisassembler::Fail;

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1366,6 +1366,15 @@ def HasVendorXqcilo
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AssemblerPredicate<(all_of FeatureVendorXqcilo),
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"'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
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// Rivos Extension(s)
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def FeatureVendorXRivosVizip
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: RISCVExperimentalExtension<0, 1, "Rivos Vector Register Zips">;
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def HasVendorXRivosVizip
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: Predicate<"Subtarget->hasVendorXRivosVizip()">,
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AssemblerPredicate<(all_of FeatureVendorXRivosVizip),
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"'XRivosVizip' (Rivos Vector Register Zips)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -2148,6 +2148,7 @@ include "RISCVInstrInfoXCV.td"
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include "RISCVInstrInfoXwch.td"
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include "RISCVInstrInfoXqci.td"
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include "RISCVInstrInfoXMips.td"
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include "RISCVInstrInfoXRivos.td"
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//===----------------------------------------------------------------------===//
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// Global ISel

‎llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td

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//===-- RISCVInstrInfoXRivos.td ----------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the vendor extensions defined by Rivos Inc.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// XRivosVizip
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXRivosVizip], DecoderNamespace = "XRivos",
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Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather,
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Inst<6-0> = OPC_CUSTOM_2.Value in {
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defm RV_VZIPEVEN_V : VALU_IV_V<"rv.vzipeven", 0b001100>;
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defm RV_VZIPODD_V : VALU_IV_V<"rv.vzipodd", 0b011100>;
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defm RV_VZIP2A_V : VALU_IV_V<"rv.vzip2a", 0b000100>;
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defm RV_VZIP2B_V : VALU_IV_V<"rv.vzip2b", 0b010100>;
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defm RV_VUNZIP2A_V : VALU_IV_V<"rv.vunzip2a", 0b001000>;
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defm RV_VUNZIP2B_V : VALU_IV_V<"rv.vunzip2b", 0b011000>;
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}

‎llvm/test/MC/RISCV/xrivosvizip-invalid.s

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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-xrivosvizip < %s 2>&1 | \
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# RUN: FileCheck %s
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# Disallowed source/dest overlap cases
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# CHECK: error: the destination vector register group cannot overlap the source vector register group
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rv.vzipeven.vv v2, v2, v3
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# CHECK: error: the destination vector register group cannot overlap the source vector register group
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rv.vzipeven.vv v3, v2, v3
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# CHECK: error: the destination vector register group cannot overlap the mask register
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rv.vzipeven.vv v0, v2, v3, v0.t

‎llvm/test/MC/RISCV/xrivosvizip-valid.s

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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-xrivosvizip < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-xrivosvizip -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-xrivosvizip < %s \
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# RUN: | llvm-objdump --mattr=+experimental-xrivosvizip -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x32]
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rv.vzipeven.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x30]
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rv.vzipeven.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x72]
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rv.vzipodd.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vzipodd.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x70]
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rv.vzipodd.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x12]
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rv.vzip2a.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x10]
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rv.vzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x52]
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rv.vzip2b.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vzip2b.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x50]
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rv.vzip2b.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x22]
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rv.vunzip2a.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vunzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x20]
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rv.vunzip2a.vv v1, v2, v3, v0.t
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# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x62]
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rv.vunzip2b.vv v1, v2, v3
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# CHECK-ASM-AND-OBJ: rv.vunzip2b.vv v1, v2, v3, v0.t
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# CHECK-ASM: encoding: [0xdb,0x80,0x21,0x60]
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rv.vunzip2b.vv v1, v2, v3, v0.t
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# Overlap between source registers *is* allowed
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# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v2
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# CHECK-ASM: encoding: [0xdb,0x00,0x21,0x32]
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rv.vzipeven.vv v1, v2, v2
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# CHECK-ASM-AND-OBJ: rv.vzipeven.vv v1, v2, v0, v0.t
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# CHECK-ASM: encoding: [0xdb,0x00,0x20,0x30]
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rv.vzipeven.vv v1, v2, v0, v0.t

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

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@@ -1129,6 +1129,7 @@ Experimental extensions
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xqcilo 0.2
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xqcilsm 0.2
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xqcisls 0.2
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xrivosvizip 0.1
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Supported Profiles
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rva20s64

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