Skip to content

Commit af2a228

Browse files
authored
[RISCV][VLOPT] Fix passthru operand info for mixed-width instructions (#126504)
After #124066 we started allowing users that are passthrus. However for widening/narrowing instructions we were returning the wrong operand info for passthru operands since it originally assumed the operand would never be a passthru. This fixes it by handling it in IsMODef.
1 parent 199c791 commit af2a228

File tree

2 files changed

+6
-5
lines changed

2 files changed

+6
-5
lines changed

llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,8 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
208208
const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MI.getDesc());
209209
const bool IsTied = RISCVII::isTiedPseudo(MI.getDesc().TSFlags);
210210

211-
bool IsMODef = MO.getOperandNo() == 0;
211+
bool IsMODef = MO.getOperandNo() == 0 ||
212+
(HasPassthru && MO.getOperandNo() == MI.getNumExplicitDefs());
212213

213214
// All mask operands have EEW=1
214215
if (isMaskOperand(MI, MO, MRI))

llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ name: vwop_vv_vd_passthru_use
9797
body: |
9898
bb.0:
9999
; CHECK-LABEL: name: vwop_vv_vd_passthru_use
100-
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
100+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
101101
; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_VV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
102102
; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
103103
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
@@ -223,7 +223,7 @@ name: vwop_wv_vd_passthru_use
223223
body: |
224224
bb.0:
225225
; CHECK-LABEL: name: vwop_wv_vd_passthru_use
226-
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
226+
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
227227
; CHECK-NEXT: early-clobber %y:vr = PseudoVWADD_WV_MF2 %x, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
228228
; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
229229
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
@@ -1115,7 +1115,7 @@ name: vmop_vv_passthru_use
11151115
body: |
11161116
bb.0:
11171117
; CHECK-LABEL: name: vmop_vv_passthru_use
1118-
; CHECK: %x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
1118+
; CHECK: %x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */
11191119
; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */
11201120
; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e8 */
11211121
%x:vrnov0 = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e1 */
@@ -1127,7 +1127,7 @@ name: vmop_vv_passthru_use_incompatible_eew
11271127
body: |
11281128
bb.0:
11291129
; CHECK-LABEL: name: vmop_vv_passthru_use_incompatible_eew
1130-
; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
1130+
; CHECK: %x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
11311131
; CHECK-NEXT: %y:vrnov0 = PseudoVMSEQ_VV_M1_MASK %x, $noreg, $noreg, $noreg, 1, 3 /* e8 */
11321132
; CHECK-NEXT: %z:vr = PseudoVMAND_MM_B8 %y, $noreg, 1, 0 /* e8 */
11331133
%x:vrnov0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0

0 commit comments

Comments
 (0)