@@ -28,6 +28,9 @@ int16_t3 test_clamp_short3(int16_t3 p0, int16_t3 p1) { return clamp(p0, p1,p1);
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// NATIVE_HALF: define [[FNATTRS]] <4 x i16> @_Z17test_clamp_short4
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// NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].sclamp.v4i16
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int16_t4 test_clamp_short4 (int16_t4 p0, int16_t4 p1) { return clamp (p0, p1,p1); }
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+ // NATIVE_HALF: define [[FNATTRS]] <4 x i16> {{.*}}test_clamp_short4_mismatch
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+ // NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].sclamp.v4i16
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+ int16_t4 test_clamp_short4_mismatch (int16_t4 p0, int16_t p1) { return clamp (p0, p0,p1); }
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// NATIVE_HALF: define [[FNATTRS]] i16 @_Z17test_clamp_ushort
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// NATIVE_HALF: call i16 @llvm.[[TARGET]].uclamp.i16(
@@ -41,6 +44,9 @@ uint16_t3 test_clamp_ushort3(uint16_t3 p0, uint16_t3 p1) { return clamp(p0, p1,p
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// NATIVE_HALF: define [[FNATTRS]] <4 x i16> @_Z18test_clamp_ushort4
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// NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].uclamp.v4i16
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uint16_t4 test_clamp_ushort4 (uint16_t4 p0, uint16_t4 p1) { return clamp (p0, p1,p1); }
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+ // NATIVE_HALF: define [[FNATTRS]] <4 x i16> {{.*}}test_clamp_ushort4_mismatch
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+ // NATIVE_HALF: call <4 x i16> @llvm.[[TARGET]].uclamp.v4i16
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+ uint16_t4 test_clamp_ushort4_mismatch (uint16_t4 p0, uint16_t p1) { return clamp (p0, p0,p1); }
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#endif
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// CHECK: define [[FNATTRS]] i32 @_Z14test_clamp_int
@@ -55,6 +61,9 @@ int3 test_clamp_int3(int3 p0, int3 p1) { return clamp(p0, p1,p1); }
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// CHECK: define [[FNATTRS]] <4 x i32> @_Z15test_clamp_int4
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// CHECK: call <4 x i32> @llvm.[[TARGET]].sclamp.v4i32
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int4 test_clamp_int4 (int4 p0, int4 p1) { return clamp (p0, p1,p1); }
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+ // CHECK: define [[FNATTRS]] <4 x i32> {{.*}}test_clamp_int4_mismatch
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+ // CHECK: call <4 x i32> @llvm.[[TARGET]].sclamp.v4i32
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+ int4 test_clamp_int4_mismatch (int4 p0, int p1) { return clamp (p0, p0,p1); }
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// CHECK: define [[FNATTRS]] i32 @_Z15test_clamp_uint
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// CHECK: call i32 @llvm.[[TARGET]].uclamp.i32(
@@ -68,6 +77,9 @@ uint3 test_clamp_uint3(uint3 p0, uint3 p1) { return clamp(p0, p1,p1); }
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// CHECK: define [[FNATTRS]] <4 x i32> @_Z16test_clamp_uint4
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// CHECK: call <4 x i32> @llvm.[[TARGET]].uclamp.v4i32
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uint4 test_clamp_uint4 (uint4 p0, uint4 p1) { return clamp (p0, p1,p1); }
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+ // CHECK: define [[FNATTRS]] <4 x i32> {{.*}}test_clamp_uint4_mismatch
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+ // CHECK: call <4 x i32> @llvm.[[TARGET]].uclamp.v4i32
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+ uint4 test_clamp_uint4_mismatch (uint4 p0, uint p1) { return clamp (p0, p0,p1); }
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// CHECK: define [[FNATTRS]] i64 @_Z15test_clamp_long
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// CHECK: call i64 @llvm.[[TARGET]].sclamp.i64(
@@ -81,6 +93,9 @@ int64_t3 test_clamp_long3(int64_t3 p0, int64_t3 p1) { return clamp(p0, p1,p1); }
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// CHECK: define [[FNATTRS]] <4 x i64> @_Z16test_clamp_long4
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// CHECK: call <4 x i64> @llvm.[[TARGET]].sclamp.v4i64
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int64_t4 test_clamp_long4 (int64_t4 p0, int64_t4 p1) { return clamp (p0, p1,p1); }
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+ // CHECK: define [[FNATTRS]] <4 x i64> {{.*}}test_clamp_long4_mismatch
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+ // CHECK: call <4 x i64> @llvm.[[TARGET]].sclamp.v4i64
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+ int64_t4 test_clamp_long4_mismatch (int64_t4 p0, int64_t p1) { return clamp (p0, p0,p1); }
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// CHECK: define [[FNATTRS]] i64 @_Z16test_clamp_ulong
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// CHECK: call i64 @llvm.[[TARGET]].uclamp.i64(
@@ -94,6 +109,9 @@ uint64_t3 test_clamp_ulong3(uint64_t3 p0, uint64_t3 p1) { return clamp(p0, p1,p1
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// CHECK: define [[FNATTRS]] <4 x i64> @_Z17test_clamp_ulong4
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// CHECK: call <4 x i64> @llvm.[[TARGET]].uclamp.v4i64
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uint64_t4 test_clamp_ulong4 (uint64_t4 p0, uint64_t4 p1) { return clamp (p0, p1,p1); }
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+ // CHECK: define [[FNATTRS]] <4 x i64> {{.*}}test_clamp_ulong4_mismatch
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+ // CHECK: call <4 x i64> @llvm.[[TARGET]].uclamp.v4i64
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+ uint64_t4 test_clamp_ulong4_mismatch (uint64_t4 p0, uint64_t p1) { return clamp (p0, p0,p1); }
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// NATIVE_HALF: define [[FNATTRS]] [[FFNATTRS]] half @_Z15test_clamp_half
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// NATIVE_HALF: call reassoc nnan ninf nsz arcp afn half @llvm.[[TARGET]].nclamp.f16(
@@ -115,6 +133,11 @@ half3 test_clamp_half3(half3 p0, half3 p1) { return clamp(p0, p1,p1); }
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// NO_HALF: define [[FNATTRS]] [[FFNATTRS]] <4 x float> @_Z16test_clamp_half4
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// NO_HALF: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.[[TARGET]].nclamp.v4f32(
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half4 test_clamp_half4 (half4 p0, half4 p1) { return clamp (p0, p1,p1); }
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+ // NATIVE_HALF: define [[FNATTRS]] [[FFNATTRS]] <4 x half> {{.*}}test_clamp_half4_mismatch
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+ // NATIVE_HALF: call reassoc nnan ninf nsz arcp afn <4 x half> @llvm.[[TARGET]].nclamp.v4f16
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+ // NO_HALF: define [[FNATTRS]] [[FFNATTRS]] <4 x float> {{.*}}test_clamp_half4_mismatch
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+ // NO_HALF: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.[[TARGET]].nclamp.v4f32(
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+ half4 test_clamp_half4_mismatch (half4 p0, half p1) { return clamp (p0, p0,p1); }
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// CHECK: define [[FNATTRS]] [[FFNATTRS]] float @_Z16test_clamp_float
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// CHECK: call reassoc nnan ninf nsz arcp afn float @llvm.[[TARGET]].nclamp.f32(
@@ -128,6 +151,9 @@ float3 test_clamp_float3(float3 p0, float3 p1) { return clamp(p0, p1,p1); }
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// CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x float> @_Z17test_clamp_float4
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// CHECK: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.[[TARGET]].nclamp.v4f32
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float4 test_clamp_float4 (float4 p0, float4 p1) { return clamp (p0, p1,p1); }
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+ // CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x float> {{.*}}test_clamp_float4_mismatch
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+ // CHECK: call reassoc nnan ninf nsz arcp afn <4 x float> @llvm.[[TARGET]].nclamp.v4f32
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+ float4 test_clamp_float4_mismatch (float4 p0, float p1) { return clamp (p0, p0,p1); }
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// CHECK: define [[FNATTRS]] [[FFNATTRS]] double @_Z17test_clamp_double
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// CHECK: call reassoc nnan ninf nsz arcp afn double @llvm.[[TARGET]].nclamp.f64(
@@ -141,3 +167,29 @@ double3 test_clamp_double3(double3 p0, double3 p1) { return clamp(p0, p1,p1); }
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// CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x double> @_Z18test_clamp_double4
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// CHECK: call reassoc nnan ninf nsz arcp afn <4 x double> @llvm.[[TARGET]].nclamp.v4f64
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double4 test_clamp_double4 (double4 p0, double4 p1) { return clamp (p0, p1,p1); }
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+ // CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x double> {{.*}}test_clamp_double4_mismatch
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+ // CHECK: call reassoc nnan ninf nsz arcp afn <4 x double> @llvm.[[TARGET]].nclamp.v4f64
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+ double4 test_clamp_double4_mismatch (double4 p0, double p1) { return clamp (p0, p0,p1); }
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+ // CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x double> {{.*}}test_clamp_double4_mismatch2
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+ // CHECK: call reassoc nnan ninf nsz arcp afn <4 x double> @llvm.[[TARGET]].nclamp.v4f64
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+ double4 test_clamp_double4_mismatch2 (double4 p0, double p1) { return clamp (p0, p1,p0); }
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+
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+ // CHECK: define [[FNATTRS]] <2 x i32> {{.*}}_overloads1
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+ // CHECK: call <2 x i32> @llvm.[[TARGET]].sclamp.v2i32
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+ int2 test_overloads1 (int2 p0, float2 p1, uint p2) { return clamp (p0, p1, p2); }
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+
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+ // CHECK: define [[FNATTRS]] [[FFNATTRS]] <2 x float> {{.*}}test_overloads2
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+ // CHECK: call reassoc nnan ninf nsz arcp afn <2 x float> @llvm.[[TARGET]].nclamp.v2f32
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+ float2 test_overloads2 (float2 p0, uint p1, int2 p2) { return clamp (p0, p1, p2); }
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+
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+ // CHECK: define [[FNATTRS]] <3 x i32> {{.*}}test_overloads3
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+ // CHECK: call <3 x i32> @llvm.[[TARGET]].uclamp.v3i32
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+ uint3 test_overloads3 (uint3 p0, int p1, float p2) { return clamp (p0, p1, p2); }
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+
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+ // CHECK: define [[FNATTRS]] [[FFNATTRS]] <4 x double> {{.*}}test_overloads4
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+ // CHECK: call reassoc nnan ninf nsz arcp afn <4 x double> @llvm.[[TARGET]].nclamp.v4f64
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+ double4 test_overloads4 (double4 p0, float4 p1, int4 p2) { return clamp (p0, p1, p2); }
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+
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+ // CHECK: define [[FNATTRS]] i32 {{.*}}test_overloads5
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+ // CHECK: call i32 @llvm.[[TARGET]].sclamp.i32(
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+ int test_overloads5 (int p0, uint p1, double p2) { return clamp (p0, p1, p2); }
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