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[VPlan] Model wrap flags directly, remove *NUW opcodes (NFC)
Model wrap flags directly using VPRecipeWithIRFlags and clean up the duplicated *NUW opcodes. D157144 will build on this and also model FMFs for VPInstruction. Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D157194
1 parent b560d5c commit af635a5

15 files changed

+96
-85
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8727,9 +8727,8 @@ static void addCanonicalIVRecipes(VPlan &Plan, Type *IdxTy, DebugLoc DL,
87278727
// IV by VF * UF.
87288728
bool HasNUW = Style == TailFoldingStyle::None;
87298729
auto *CanonicalIVIncrement =
8730-
new VPInstruction(HasNUW ? VPInstruction::CanonicalIVIncrementNUW
8731-
: VPInstruction::CanonicalIVIncrement,
8732-
{CanonicalIVPHI}, DL, "index.next");
8730+
new VPInstruction(VPInstruction::CanonicalIVIncrement, {CanonicalIVPHI},
8731+
{HasNUW, false}, DL, "index.next");
87338732
CanonicalIVPHI->addOperand(CanonicalIVIncrement);
87348733

87358734
VPBasicBlock *EB = TopRegion->getExitingBasicBlock();
@@ -8742,9 +8741,8 @@ static void addCanonicalIVRecipes(VPlan &Plan, Type *IdxTy, DebugLoc DL,
87428741
// we have to take unrolling into account. Each part needs to start at
87438742
// Part * VF
87448743
auto *CanonicalIVIncrementParts =
8745-
new VPInstruction(HasNUW ? VPInstruction::CanonicalIVIncrementForPartNUW
8746-
: VPInstruction::CanonicalIVIncrementForPart,
8747-
{StartV}, DL, "index.part.next");
8744+
new VPInstruction(VPInstruction::CanonicalIVIncrementForPart, {StartV},
8745+
{HasNUW, false}, DL, "index.part.next");
87488746
VecPreheader->appendRecipe(CanonicalIVIncrementParts);
87498747

87508748
// Create the ActiveLaneMask instruction using the correct start values.
@@ -8781,9 +8779,8 @@ static void addCanonicalIVRecipes(VPlan &Plan, Type *IdxTy, DebugLoc DL,
87818779

87828780
// Create the active lane mask for the next iteration of the loop.
87838781
CanonicalIVIncrementParts =
8784-
new VPInstruction(HasNUW ? VPInstruction::CanonicalIVIncrementForPartNUW
8785-
: VPInstruction::CanonicalIVIncrementForPart,
8786-
{IncrementValue}, DL);
8782+
new VPInstruction(VPInstruction::CanonicalIVIncrementForPart,
8783+
{IncrementValue}, {HasNUW, false}, DL);
87878784
EB->appendRecipe(CanonicalIVIncrementParts);
87888785

87898786
auto *ALM = new VPInstruction(VPInstruction::ActiveLaneMask,

‎llvm/lib/Transforms/Vectorize/VPlan.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -763,11 +763,9 @@ void VPlan::prepareToExecute(Value *TripCountV, Value *VectorTripCountV,
763763
return true;
764764
auto *VPI = cast<VPInstruction>(U);
765765
return VPI->getOpcode() ==
766-
VPInstruction::CanonicalIVIncrement ||
767-
VPI->getOpcode() ==
768-
VPInstruction::CanonicalIVIncrementNUW;
766+
VPInstruction::CanonicalIVIncrement;
769767
}) &&
770-
"the canonical IV should only be used by its increments or "
768+
"the canonical IV should only be used by its increment or "
771769
"ScalarIVSteps when resetting the start value");
772770
IV->setOperand(0, VPV);
773771
}

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 35 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -820,10 +820,16 @@ class VPRecipeWithIRFlags : public VPRecipeBase {
820820
FPMathOp,
821821
Other
822822
};
823+
824+
public:
823825
struct WrapFlagsTy {
824826
char HasNUW : 1;
825827
char HasNSW : 1;
828+
829+
WrapFlagsTy(bool HasNUW, bool HasNSW) : HasNUW(HasNUW), HasNSW(HasNSW) {}
826830
};
831+
832+
private:
827833
struct ExactFlagsTy {
828834
char IsExact : 1;
829835
};
@@ -863,8 +869,7 @@ class VPRecipeWithIRFlags : public VPRecipeBase {
863869
: VPRecipeWithIRFlags(SC, Operands) {
864870
if (auto *Op = dyn_cast<OverflowingBinaryOperator>(&I)) {
865871
OpType = OperationType::OverflowingBinOp;
866-
WrapFlags.HasNUW = Op->hasNoUnsignedWrap();
867-
WrapFlags.HasNSW = Op->hasNoSignedWrap();
872+
WrapFlags = {Op->hasNoUnsignedWrap(), Op->hasNoSignedWrap()};
868873
} else if (auto *Op = dyn_cast<PossiblyExactOperator>(&I)) {
869874
OpType = OperationType::PossiblyExactOp;
870875
ExactFlags.IsExact = Op->isExact();
@@ -884,8 +889,15 @@ class VPRecipeWithIRFlags : public VPRecipeBase {
884889
}
885890
}
886891

892+
template <typename IterT>
893+
VPRecipeWithIRFlags(const unsigned char SC, IterT Operands,
894+
WrapFlagsTy WrapFlags)
895+
: VPRecipeBase(SC, Operands), OpType(OperationType::OverflowingBinOp),
896+
WrapFlags(WrapFlags) {}
897+
887898
static inline bool classof(const VPRecipeBase *R) {
888-
return R->getVPDefID() == VPRecipeBase::VPWidenSC ||
899+
return R->getVPDefID() == VPRecipeBase::VPInstructionSC ||
900+
R->getVPDefID() == VPRecipeBase::VPWidenSC ||
889901
R->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
890902
R->getVPDefID() == VPRecipeBase::VPReplicateSC;
891903
}
@@ -949,6 +961,18 @@ class VPRecipeWithIRFlags : public VPRecipeBase {
949961

950962
FastMathFlags getFastMathFlags() const;
951963

964+
bool hasNoUnsignedWrap() const {
965+
assert(OpType == OperationType::OverflowingBinOp &&
966+
"recipe doesn't have a NUW flag");
967+
return WrapFlags.HasNUW;
968+
}
969+
970+
bool hasNoSignedWrap() const {
971+
assert(OpType == OperationType::OverflowingBinOp &&
972+
"recipe doesn't have a NUW flag");
973+
return WrapFlags.HasNSW;
974+
}
975+
952976
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
953977
void printFlags(raw_ostream &O) const;
954978
#endif
@@ -958,7 +982,7 @@ class VPRecipeWithIRFlags : public VPRecipeBase {
958982
/// While as any Recipe it may generate a sequence of IR instructions when
959983
/// executed, these instructions would always form a single-def expression as
960984
/// the VPInstruction is also a single def-use vertex.
961-
class VPInstruction : public VPRecipeBase, public VPValue {
985+
class VPInstruction : public VPRecipeWithIRFlags, public VPValue {
962986
friend class VPlanSlp;
963987

964988
public:
@@ -974,11 +998,9 @@ class VPInstruction : public VPRecipeBase, public VPValue {
974998
ActiveLaneMask,
975999
CalculateTripCountMinusVF,
9761000
CanonicalIVIncrement,
977-
CanonicalIVIncrementNUW,
978-
// The next two are similar to the above, but instead increment the
1001+
// The next op is similar to the above, but instead increment the
9791002
// canonical IV separately for each unrolled part.
9801003
CanonicalIVIncrementForPart,
981-
CanonicalIVIncrementForPartNUW,
9821004
BranchOnCount,
9831005
BranchOnCond
9841006
};
@@ -1004,13 +1026,18 @@ class VPInstruction : public VPRecipeBase, public VPValue {
10041026
public:
10051027
VPInstruction(unsigned Opcode, ArrayRef<VPValue *> Operands, DebugLoc DL,
10061028
const Twine &Name = "")
1007-
: VPRecipeBase(VPDef::VPInstructionSC, Operands), VPValue(this),
1029+
: VPRecipeWithIRFlags(VPDef::VPInstructionSC, Operands), VPValue(this),
10081030
Opcode(Opcode), DL(DL), Name(Name.str()) {}
10091031

10101032
VPInstruction(unsigned Opcode, std::initializer_list<VPValue *> Operands,
10111033
DebugLoc DL = {}, const Twine &Name = "")
10121034
: VPInstruction(Opcode, ArrayRef<VPValue *>(Operands), DL, Name) {}
10131035

1036+
VPInstruction(unsigned Opcode, std::initializer_list<VPValue *> Operands,
1037+
WrapFlagsTy WrapFlags, DebugLoc DL = {}, const Twine &Name = "")
1038+
: VPRecipeWithIRFlags(VPDef::VPInstructionSC, Operands, WrapFlags),
1039+
VPValue(this), Opcode(Opcode), DL(DL), Name(Name.str()) {}
1040+
10141041
VP_CLASSOF_IMPL(VPDef::VPInstructionSC)
10151042

10161043
VPInstruction *clone() const {
@@ -1079,9 +1106,7 @@ class VPInstruction : public VPRecipeBase, public VPValue {
10791106
case VPInstruction::ActiveLaneMask:
10801107
case VPInstruction::CalculateTripCountMinusVF:
10811108
case VPInstruction::CanonicalIVIncrement:
1082-
case VPInstruction::CanonicalIVIncrementNUW:
10831109
case VPInstruction::CanonicalIVIncrementForPart:
1084-
case VPInstruction::CanonicalIVIncrementForPartNUW:
10851110
case VPInstruction::BranchOnCount:
10861111
return true;
10871112
};

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 8 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -299,31 +299,28 @@ Value *VPInstruction::generateInstruction(VPTransformState &State,
299299
Value *Zero = ConstantInt::get(ScalarTC->getType(), 0);
300300
return Builder.CreateSelect(Cmp, Sub, Zero);
301301
}
302-
case VPInstruction::CanonicalIVIncrement:
303-
case VPInstruction::CanonicalIVIncrementNUW: {
302+
case VPInstruction::CanonicalIVIncrement: {
304303
if (Part == 0) {
305-
bool IsNUW = getOpcode() == VPInstruction::CanonicalIVIncrementNUW;
306304
auto *Phi = State.get(getOperand(0), 0);
307305
// The loop step is equal to the vectorization factor (num of SIMD
308306
// elements) times the unroll factor (num of SIMD instructions).
309307
Value *Step =
310308
createStepForVF(Builder, Phi->getType(), State.VF, State.UF);
311-
return Builder.CreateAdd(Phi, Step, Name, IsNUW, false);
309+
return Builder.CreateAdd(Phi, Step, Name, hasNoUnsignedWrap(),
310+
hasNoSignedWrap());
312311
}
313312
return State.get(this, 0);
314313
}
315314

316-
case VPInstruction::CanonicalIVIncrementForPart:
317-
case VPInstruction::CanonicalIVIncrementForPartNUW: {
318-
bool IsNUW = getOpcode() == VPInstruction::CanonicalIVIncrementForPartNUW;
315+
case VPInstruction::CanonicalIVIncrementForPart: {
319316
auto *IV = State.get(getOperand(0), VPIteration(0, 0));
320317
if (Part == 0)
321318
return IV;
322319

323320
// The canonical IV is incremented by the vectorization factor (num of SIMD
324321
// elements) times the unroll part.
325322
Value *Step = createStepForVF(Builder, IV->getType(), State.VF, Part);
326-
return Builder.CreateAdd(IV, Step, Name, IsNUW, false);
323+
return Builder.CreateAdd(IV, Step, Name, hasNoUnsignedWrap(), false);
327324
}
328325
case VPInstruction::BranchOnCond: {
329326
if (Part != 0)
@@ -425,9 +422,6 @@ void VPInstruction::print(raw_ostream &O, const Twine &Indent,
425422
case VPInstruction::CanonicalIVIncrement:
426423
O << "VF * UF +";
427424
break;
428-
case VPInstruction::CanonicalIVIncrementNUW:
429-
O << "VF * UF +(nuw)";
430-
break;
431425
case VPInstruction::BranchOnCond:
432426
O << "branch-on-cond";
433427
break;
@@ -437,9 +431,6 @@ void VPInstruction::print(raw_ostream &O, const Twine &Indent,
437431
case VPInstruction::CanonicalIVIncrementForPart:
438432
O << "VF * Part +";
439433
break;
440-
case VPInstruction::CanonicalIVIncrementForPartNUW:
441-
O << "VF * Part +(nuw)";
442-
break;
443434
case VPInstruction::BranchOnCount:
444435
O << "branch-on-count";
445436
break;
@@ -448,8 +439,7 @@ void VPInstruction::print(raw_ostream &O, const Twine &Indent,
448439
}
449440

450441
O << FMF;
451-
if (getNumOperands() > 0)
452-
O << " ";
442+
printFlags(O);
453443
printOperands(O, SlotTracker);
454444

455445
if (DL) {
@@ -608,7 +598,8 @@ void VPRecipeWithIRFlags::printFlags(raw_ostream &O) const {
608598
case OperationType::Other:
609599
break;
610600
}
611-
O << " ";
601+
if (getNumOperands() > 0)
602+
O << " ";
612603
}
613604
#endif
614605

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ target triple = "aarch64-unknown-linux-gnu"
2525
; CHECK-NEXT: WIDEN ir<%lv> = load ir<%ptr.iv.2>
2626
; CHECK-NEXT: WIDEN ir<%add> = add ir<%lv>, ir<1>
2727
; CHECK-NEXT: WIDEN store ir<%ptr.iv.2>, ir<%add>
28-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
28+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
2929
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
3030
; CHECK-NEXT: No successors
3131
; CHECK-NEXT: }

‎llvm/test/Transforms/LoopVectorize/AArch64/synthesize-mask-for-call.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,8 @@ target triple = "aarch64-unknown-linux-gnu"
2525
; CHECK-NEXT: REPLICATE ir<%call> = call @foo(ir<%load>)
2626
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[STEPS]]>
2727
; CHECK-NEXT: WIDEN store ir<%arrayidx>, ir<%call>
28-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
29-
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
28+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
29+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
3030
; CHECK-NEXT: No successors
3131
; CHECK-NEXT: }
3232
; CHECK-NEXT: Successor(s): middle.block
@@ -51,7 +51,7 @@ target triple = "aarch64-unknown-linux-gnu"
5151
; CHECK-NEXT: WIDEN-CALL ir<%call> = call @foo(ir<%load>) (using library function: foo_vector_fixed4_nomask)
5252
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[STEPS]]>
5353
; CHECK-NEXT: WIDEN store ir<%arrayidx>, ir<%call>
54-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
54+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
5555
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
5656
; CHECK-NEXT: No successors
5757
; CHECK-NEXT: }
@@ -82,7 +82,7 @@ target triple = "aarch64-unknown-linux-gnu"
8282
; CHECK-NEXT: WIDEN-CALL ir<%call> = call @foo(ir<%load>) (using library function: foo_vector_fixed2_nomask)
8383
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[STEPS]]>
8484
; CHECK-NEXT: WIDEN store ir<%arrayidx>, ir<%call>
85-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXST:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
85+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXST:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
8686
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
8787
; CHECK-NEXT: No successors
8888
; CHECK-NEXT: }
@@ -108,7 +108,7 @@ target triple = "aarch64-unknown-linux-gnu"
108108
; CHECK-NEXT: WIDEN-CALL ir<%call> = call @foo(ir<%load>, ir<true>) (using library function: foo_vector_fixed4_mask)
109109
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[STEPS]]>
110110
; CHECK-NEXT: WIDEN store ir<%arrayidx>, ir<%call>
111-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
111+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
112112
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
113113
; CHECK-NEXT: No successors
114114
; CHECK-NEXT: }
@@ -138,8 +138,8 @@ target triple = "aarch64-unknown-linux-gnu"
138138
; CHECK-NEXT: WIDEN-CALL ir<%call> = call @foo(ir<%load>) (using library function: foo_vector_fixed2_nomask)
139139
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[STEPS]]>
140140
; CHECK-NEXT: WIDEN store ir<%arrayidx>, ir<%call>
141-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
142-
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
141+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
142+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
143143
; CHECK-NEXT: No successors
144144
; CHECK-NEXT: }
145145
; CHECK-NEXT: Successor(s): middle.block
@@ -164,7 +164,7 @@ target triple = "aarch64-unknown-linux-gnu"
164164
; CHECK-NEXT: WIDEN-CALL ir<%call> = call @foo(ir<%load>) (using library function: foo_vector_fixed4_nomask)
165165
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%a>, vp<[[STEPS]]>
166166
; CHECK-NEXT: WIDEN store ir<%arrayidx>, ir<%call>
167-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
167+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
168168
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
169169
; CHECK-NEXT: No successors
170170
; CHECK-NEXT: }

‎llvm/test/Transforms/LoopVectorize/AArch64/widen-call-with-intrinsic-or-libfunc.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ target triple = "arm64-apple-ios"
2323
; CHECK-NEXT: WIDEN-CALL ir<%s> = call @llvm.sin.f64(ir<%conv>) (using library function: __simd_sin_v2f64)
2424
; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr inbounds ir<%dst>, vp<[[STEPS]]>
2525
; CHECK-NEXT: REPLICATE store ir<%s>, ir<%gep.dst>
26-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
26+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
2727
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
2828
; CHECK-NEXT: No successors
2929
; CHECK-NEXT: }
@@ -50,7 +50,7 @@ target triple = "arm64-apple-ios"
5050
; CHECK-NEXT: WIDEN-CALL ir<%s> = call @llvm.sin.f64(ir<%conv>) (using vector intrinsic)
5151
; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr inbounds ir<%dst>, vp<[[STEPS]]>
5252
; CHECK-NEXT: REPLICATE store ir<%s>, ir<%gep.dst>
53-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
53+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
5454
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
5555
; CHECK-NEXT: No successors
5656
; CHECK-NEXT: }

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
7070
; CHECK-NEXT: WIDEN ir<%add9> = add ir<%1>, ir<1>
7171
; CHECK-NEXT: CLONE ir<%arrayidx3> = getelementptr inbounds ir<%A>, ir<%idxprom>
7272
; CHECK-NEXT: WIDEN store ir<%arrayidx3>, ir<%add9>
73-
; CHECK-NEXT: EMIT vp<%11> = VF * UF +(nuw) vp<%2>
73+
; CHECK-NEXT: EMIT vp<%11> = VF * UF + nuw vp<%2>
7474
; CHECK-NEXT: EMIT branch-on-count vp<%11>, vp<%0>
7575
; CHECK-NEXT: No successors
7676
; CHECK-NEXT: }
@@ -206,7 +206,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
206206
; CHECK-NEXT: WIDEN ir<%conv1> = fadd ir<%1>, ir<1.000000e+00>
207207
; CHECK-NEXT: CLONE ir<%arrayidx3> = getelementptr inbounds ir<%A>, ir<%idxprom>
208208
; CHECK-NEXT: WIDEN store ir<%arrayidx3>, ir<%conv1>
209-
; CHECK-NEXT: EMIT vp<%11> = VF * UF +(nuw) vp<%2>
209+
; CHECK-NEXT: EMIT vp<%11> = VF * UF + nuw vp<%2>
210210
; CHECK-NEXT: EMIT branch-on-count vp<%11>, vp<%0>
211211
; CHECK-NEXT: No successors
212212
; CHECK-NEXT: }

‎llvm/test/Transforms/LoopVectorize/first-order-recurrence-chains-vplan.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,8 @@ define void @test_chained_first_order_recurrences_1(ptr %ptr) {
2323
; CHECK-NEXT: EMIT vp<[[FOR2_SPLICE:%.+]]> = first-order splice ir<%for.2>, vp<[[FOR1_SPLICE]]>
2424
; CHECK-NEXT: WIDEN ir<%add> = add vp<[[FOR1_SPLICE]]>, vp<[[FOR2_SPLICE]]>
2525
; CHECK-NEXT: WIDEN store ir<%gep.ptr>, ir<%add>
26-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
27-
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
26+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
27+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
2828
; CHECK-NEXT: No successors
2929
; CHECK-NEXT: }
3030
; CHECK-NEXT: Successor(s): middle.block
@@ -76,8 +76,8 @@ define void @test_chained_first_order_recurrences_3(ptr %ptr) {
7676
; CHECK-NEXT: WIDEN ir<%add.1> = add vp<[[FOR1_SPLICE]]>, vp<[[FOR2_SPLICE]]>
7777
; CHECK-NEXT: WIDEN ir<%add.2> = add ir<%add.1>, vp<[[FOR3_SPLICE]]>
7878
; CHECK-NEXT: WIDEN store ir<%gep.ptr>, ir<%add.2>
79-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
80-
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
79+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
80+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
8181
; CHECK-NEXT: No successors
8282
; CHECK-NEXT: }
8383
; CHECK-NEXT: Successor(s): middle.block

‎llvm/test/Transforms/LoopVectorize/interleave-and-scalarize-only.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,8 @@
2323
; DBG-NEXT: CLONE ir<%min> = call @llvm.smin.i32(vp<[[IV_STEPS]]>, ir<65535>)
2424
; DBG-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%dst>, vp<[[IV_STEPS]]>
2525
; DBG-NEXT: CLONE store ir<%min>, ir<%arrayidx>
26-
; DBG-NEXT: EMIT vp<[[INC:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
27-
; DBG-NEXT: EMIT branch-on-count vp<[[INC]]>, vp<[[VEC_TC]]>
26+
; DBG-NEXT: EMIT vp<[[INC:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
27+
; DBG-NEXT: EMIT branch-on-count vp<[[INC]]>, vp<[[VEC_TC]]>
2828
; DBG-NEXT: No successors
2929
; DBG-NEXT: }
3030
;
@@ -100,8 +100,8 @@ declare i32 @llvm.smin.i32(i32, i32)
100100
; DBG-NEXT: Successor(s): cond.false.1
101101
; DBG-EMPTY:
102102
; DBG-NEXT: cond.false.1:
103-
; DBG-NEXT: EMIT vp<[[CAN_IV_INC:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
104-
; DBG-NEXT: EMIT branch-on-count vp<[[CAN_IV_INC]]>, vp<[[VEC_TC]]>
103+
; DBG-NEXT: EMIT vp<[[CAN_IV_INC:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
104+
; DBG-NEXT: EMIT branch-on-count vp<[[CAN_IV_INC]]>, vp<[[VEC_TC]]>
105105
; DBG-NEXT: No successors
106106
; DBG-NEXT: }
107107
; DBG-NEXT: Successor(s): middle.block
@@ -191,8 +191,8 @@ exit:
191191
; DBG-NEXT: vp<[[SCALAR_STEPS]]> = SCALAR-STEPS vp<[[DERIVED_IV]]>, ir<1>
192192
; DBG-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%for>, vp<[[SCALAR_STEPS]]>
193193
; DBG-NEXT: CLONE store vp<[[SPLICE]]>, ir<%dst>
194-
; DBG-NEXT: EMIT vp<[[IV_INC:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
195-
; DBG-NEXT: EMIT branch-on-count vp<[[IV_INC]]>, vp<[[VTC]]>
194+
; DBG-NEXT: EMIT vp<[[IV_INC:%.+]]> = VF * UF + nuw vp<[[CAN_IV]]>
195+
; DBG-NEXT: EMIT branch-on-count vp<[[IV_INC]]>, vp<[[VTC]]>
196196
; DBG-NEXT: No successors
197197
; DBG-NEXT: }
198198
; DBG-NEXT: Successor(s): middle.block

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