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[FrameLowering] Use MCRegister instead of Register in CalleeSavedInfo. NFC (#128095)
Callee saved registers should always be phyiscal registers. They are often passed directly to other functions that take MCRegister like getMinimalPhysRegClass or TargetRegisterClass::contains. Unfortunately, sometimes the MCRegister is compared to a Register which gave an ambiguous comparison error when the MCRegister is on the LHS. Adding a MCRegister==Register comparison operator created more ambiguous comparison errors elsewhere. These cases were usually comparing against a base or frame pointer register that is a physical register in a Register. For those I added an explicit conversion of Register to MCRegister to fix the error.
1 parent 5815990 commit af64f0a

24 files changed

+97
-99
lines changed

‎llvm/include/llvm/CodeGen/MachineFrameInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ class AllocaInst;
3232
/// Callee saved reg can also be saved to a different register rather than
3333
/// on the stack by setting DstReg instead of FrameIdx.
3434
class CalleeSavedInfo {
35-
Register Reg;
35+
MCRegister Reg;
3636
union {
3737
int FrameIdx;
3838
unsigned DstReg;
@@ -58,7 +58,7 @@ class CalleeSavedInfo {
5858
explicit CalleeSavedInfo(unsigned R, int FI = 0) : Reg(R), FrameIdx(FI) {}
5959

6060
// Accessors.
61-
Register getReg() const { return Reg; }
61+
MCRegister getReg() const { return Reg; }
6262
int getFrameIdx() const { return FrameIdx; }
6363
unsigned getDstReg() const { return DstReg; }
6464
void setFrameIdx(int FI) {

‎llvm/lib/CodeGen/LivePhysRegs.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -301,7 +301,7 @@ void llvm::recomputeLivenessFlags(MachineBasicBlock &MBB) {
301301
// the last instruction in the block.
302302
if (MI.isReturn() && MFI.isCalleeSavedInfoValid()) {
303303
for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
304-
if (Info.getReg() == Reg) {
304+
if (Info.getReg() == Reg.asMCReg()) {
305305
IsNotLive = !Info.isRestored();
306306
break;
307307
}

‎llvm/lib/CodeGen/PrologEpilogInserter.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -481,7 +481,7 @@ static void assignCalleeSavedSpillSlots(MachineFunction &F,
481481
if (CS.isSpilledToReg())
482482
continue;
483483

484-
unsigned Reg = CS.getReg();
484+
MCRegister Reg = CS.getReg();
485485
const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
486486

487487
int FrameIdx;
@@ -570,7 +570,7 @@ static void updateLiveness(MachineFunction &MF) {
570570
MachineRegisterInfo &MRI = MF.getRegInfo();
571571
for (const CalleeSavedInfo &I : CSI) {
572572
for (MachineBasicBlock *MBB : Visited) {
573-
MCPhysReg Reg = I.getReg();
573+
MCRegister Reg = I.getReg();
574574
// Add the callee-saved register as live-in.
575575
// It's killed at the spill.
576576
if (!MRI.isReserved(Reg) && !MBB->isLiveIn(Reg))
@@ -605,7 +605,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
605605
if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
606606
for (const CalleeSavedInfo &CS : CSI) {
607607
// Insert the spill to the stack frame.
608-
unsigned Reg = CS.getReg();
608+
MCRegister Reg = CS.getReg();
609609

610610
if (CS.isSpilledToReg()) {
611611
BuildMI(SaveBlock, I, DebugLoc(),
@@ -634,7 +634,7 @@ static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
634634

635635
if (!TFI->restoreCalleeSavedRegisters(RestoreBlock, I, CSI, TRI)) {
636636
for (const CalleeSavedInfo &CI : reverse(CSI)) {
637-
unsigned Reg = CI.getReg();
637+
MCRegister Reg = CI.getReg();
638638
if (CI.isSpilledToReg()) {
639639
BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg)
640640
.addReg(CI.getDstReg(), getKillRegState(true));

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -655,7 +655,7 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
655655
// Not all unwinders may know about SVE registers, so assume the lowest
656656
// common demoninator.
657657
assert(!Info.isSpilledToReg() && "Spilling to registers not implemented");
658-
unsigned Reg = Info.getReg();
658+
MCRegister Reg = Info.getReg();
659659
if (!static_cast<const AArch64RegisterInfo &>(TRI).regNeedsCFI(Reg, Reg))
660660
continue;
661661

@@ -716,7 +716,7 @@ void AArch64FrameLowering::resetCFIToInitialState(
716716
const std::vector<CalleeSavedInfo> &CSI =
717717
MF.getFrameInfo().getCalleeSavedInfo();
718718
for (const auto &Info : CSI) {
719-
unsigned Reg = Info.getReg();
719+
MCRegister Reg = Info.getReg();
720720
if (!TRI.regNeedsCFI(Reg, Reg))
721721
continue;
722722
insertCFISameValue(CFIDesc, MF, MBB, InsertPt,
@@ -744,7 +744,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
744744
(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
745745
continue;
746746

747-
unsigned Reg = Info.getReg();
747+
MCRegister Reg = Info.getReg();
748748
if (SVE &&
749749
!static_cast<const AArch64RegisterInfo &>(TRI).regNeedsCFI(Reg, Reg))
750750
continue;
@@ -3051,7 +3051,7 @@ static void computeCalleeSaveRegisterPairs(
30513051
int Scale = TRI->getSpillSize(*RPI.RC);
30523052
// Add the next reg to the pair if it is in the same register class.
30533053
if (unsigned(i + RegInc) < Count && !AFI->hasStackHazardSlotIndex()) {
3054-
Register NextReg = CSI[i + RegInc].getReg();
3054+
MCRegister NextReg = CSI[i + RegInc].getReg();
30553055
bool IsFirst = i == FirstReg;
30563056
switch (RPI.Type) {
30573057
case RegPairInfo::GPR:
@@ -3986,7 +3986,7 @@ bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
39863986
Register LastReg = 0;
39873987
int HazardSlotIndex = std::numeric_limits<int>::max();
39883988
for (auto &CS : CSI) {
3989-
Register Reg = CS.getReg();
3989+
MCRegister Reg = CS.getReg();
39903990
const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
39913991

39923992
// Create a hazard slot as we switch between GPR and FPR CSRs.

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,8 @@ AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT, unsigned HwMode)
4949
/// callee-saves required by the base ABI. For the SVE registers z8-z15 only the
5050
/// lower 64-bits (d8-d15) need to be saved. The lower 64-bits subreg is
5151
/// returned in \p RegToUseForCFI.
52-
bool AArch64RegisterInfo::regNeedsCFI(unsigned Reg,
53-
unsigned &RegToUseForCFI) const {
52+
bool AArch64RegisterInfo::regNeedsCFI(MCRegister Reg,
53+
MCRegister &RegToUseForCFI) const {
5454
if (AArch64::PPRRegClass.contains(Reg))
5555
return false;
5656

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
140140
const LiveRegMatrix *Matrix) const override;
141141

142142
unsigned getLocalAddressRegister(const MachineFunction &MF) const;
143-
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
143+
bool regNeedsCFI(MCRegister Reg, MCRegister &RegToUseForCFI) const;
144144

145145
/// SrcRC and DstRC will be morphed into NewRC if this returns true
146146
bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,

‎llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1719,11 +1719,12 @@ bool SIFrameLowering::assignCalleeSavedSpillSlots(
17191719
NumModifiedRegs++;
17201720

17211721
for (auto &CS : CSI) {
1722-
if (CS.getReg() == FramePtrReg && SGPRForFPSaveRestoreCopy) {
1722+
if (CS.getReg() == FramePtrReg.asMCReg() && SGPRForFPSaveRestoreCopy) {
17231723
CS.setDstReg(SGPRForFPSaveRestoreCopy);
17241724
if (--NumModifiedRegs)
17251725
break;
1726-
} else if (CS.getReg() == BasePtrReg && SGPRForBPSaveRestoreCopy) {
1726+
} else if (CS.getReg() == BasePtrReg.asMCReg() &&
1727+
SGPRForBPSaveRestoreCopy) {
17271728
CS.setDstReg(SGPRForBPSaveRestoreCopy);
17281729
if (--NumModifiedRegs)
17291730
break;

‎llvm/lib/Target/ARC/ARCFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -219,7 +219,7 @@ void ARCFrameLowering::emitPrologue(MachineFunction &MF,
219219
}
220220
// CFI for the rest of the registers.
221221
for (const auto &Entry : CSI) {
222-
unsigned Reg = Entry.getReg();
222+
MCRegister Reg = Entry.getReg();
223223
int FI = Entry.getFrameIdx();
224224
// Skip BLINK and FP.
225225
if ((hasFP(MF) && Reg == ARC::FP) || (MFI.hasCalls() && Reg == ARC::BLINK))

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -952,13 +952,13 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
952952
SpillArea FramePtrSpillArea = SpillArea::GPRCS1;
953953
bool BeforeFPPush = true;
954954
for (const CalleeSavedInfo &I : CSI) {
955-
Register Reg = I.getReg();
955+
MCRegister Reg = I.getReg();
956956
int FI = I.getFrameIdx();
957957

958958
SpillArea Area = getSpillArea(Reg, PushPopSplit,
959959
AFI->getNumAlignedDPRCS2Regs(), RegInfo);
960960

961-
if (Reg == FramePtr) {
961+
if (Reg == FramePtr.asMCReg()) {
962962
FramePtrSpillFI = FI;
963963
FramePtrSpillArea = Area;
964964
}
@@ -1280,7 +1280,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
12801280
// recording where each register ended up:
12811281
if (!NeedsWinCFI) {
12821282
for (const auto &Entry : reverse(CSI)) {
1283-
Register Reg = Entry.getReg();
1283+
MCRegister Reg = Entry.getReg();
12841284
int FI = Entry.getFrameIdx();
12851285
MachineBasicBlock::iterator CFIPos;
12861286
switch (getSpillArea(Reg, PushPopSplit, AFI->getNumAlignedDPRCS2Regs(),
@@ -1668,7 +1668,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
16681668
while (i != 0) {
16691669
unsigned LastReg = 0;
16701670
for (; i != 0; --i) {
1671-
Register Reg = CSI[i-1].getReg();
1671+
MCRegister Reg = CSI[i-1].getReg();
16721672
if (!Func(Reg))
16731673
continue;
16741674

@@ -1761,7 +1761,7 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
17611761
bool DeleteRet = false;
17621762
for (; i != 0; --i) {
17631763
CalleeSavedInfo &Info = CSI[i-1];
1764-
Register Reg = Info.getReg();
1764+
MCRegister Reg = Info.getReg();
17651765
if (!Func(Reg))
17661766
continue;
17671767

@@ -3003,7 +3003,7 @@ bool ARMFrameLowering::assignCalleeSavedSpillSlots(
30033003
// LR, R7, R6, R5, R4, <R12>, R11, R10, R9, R8, D15-D8
30043004
CSI.insert(find_if(CSI,
30053005
[=](const auto &CS) {
3006-
Register Reg = CS.getReg();
3006+
MCRegister Reg = CS.getReg();
30073007
return Reg == ARM::R10 || Reg == ARM::R11 ||
30083008
Reg == ARM::R8 || Reg == ARM::R9 ||
30093009
ARM::DPRRegClass.contains(Reg);
@@ -3021,7 +3021,7 @@ bool ARMFrameLowering::assignCalleeSavedSpillSlots(
30213021
"address.");
30223022
CSI.insert(find_if(CSI,
30233023
[=](const auto &CS) {
3024-
Register Reg = CS.getReg();
3024+
MCRegister Reg = CS.getReg();
30253025
return Reg != ARM::LR;
30263026
}),
30273027
CalleeSavedInfo(ARM::R12));

‎llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -210,9 +210,9 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
210210
bool HasFrameRecordArea = hasFP(MF) && ARM::hGPRRegClass.contains(FramePtr);
211211

212212
for (const CalleeSavedInfo &I : CSI) {
213-
Register Reg = I.getReg();
213+
MCRegister Reg = I.getReg();
214214
int FI = I.getFrameIdx();
215-
if (Reg == FramePtr)
215+
if (Reg == FramePtr.asMCReg())
216216
FramePtrSpillFI = FI;
217217
switch (Reg) {
218218
case ARM::R11:
@@ -371,7 +371,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
371371
.setMIFlags(MachineInstr::FrameSetup);
372372
}
373373
for (const CalleeSavedInfo &I : CSI) {
374-
Register Reg = I.getReg();
374+
MCRegister Reg = I.getReg();
375375
int FI = I.getFrameIdx();
376376
switch (Reg) {
377377
case ARM::R8:
@@ -403,7 +403,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
403403
if (GPRCS2Size > 0) {
404404
MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
405405
for (auto &I : CSI) {
406-
Register Reg = I.getReg();
406+
MCRegister Reg = I.getReg();
407407
int FI = I.getFrameIdx();
408408
switch (Reg) {
409409
case ARM::R8:
@@ -432,8 +432,8 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
432432
// at this point in the prologue, so pick one.
433433
unsigned ScratchRegister = ARM::NoRegister;
434434
for (auto &I : CSI) {
435-
Register Reg = I.getReg();
436-
if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
435+
MCRegister Reg = I.getReg();
436+
if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr.asMCReg())) {
437437
ScratchRegister = Reg;
438438
break;
439439
}
@@ -552,8 +552,8 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
552552
unsigned ScratchRegister = ARM::NoRegister;
553553
bool HasFP = hasFP(MF);
554554
for (auto &I : MFI.getCalleeSavedInfo()) {
555-
Register Reg = I.getReg();
556-
if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
555+
MCRegister Reg = I.getReg();
556+
if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr.asMCReg())) {
557557
ScratchRegister = Reg;
558558
break;
559559
}
@@ -1118,8 +1118,8 @@ bool Thumb1FrameLowering::spillCalleeSavedRegisters(
11181118
std::set<Register> FrameRecord;
11191119
std::set<Register> SpilledGPRs;
11201120
for (const CalleeSavedInfo &I : CSI) {
1121-
Register Reg = I.getReg();
1122-
if (NeedsFrameRecordPush && (Reg == FPReg || Reg == ARM::LR))
1121+
MCRegister Reg = I.getReg();
1122+
if (NeedsFrameRecordPush && (Reg == FPReg.asMCReg() || Reg == ARM::LR))
11231123
FrameRecord.insert(Reg);
11241124
else
11251125
SpilledGPRs.insert(Reg);
@@ -1206,8 +1206,8 @@ bool Thumb1FrameLowering::restoreCalleeSavedRegisters(
12061206
std::set<Register> FrameRecord;
12071207
std::set<Register> SpilledGPRs;
12081208
for (CalleeSavedInfo &I : CSI) {
1209-
Register Reg = I.getReg();
1210-
if (NeedsFrameRecordPop && (Reg == FPReg || Reg == ARM::LR))
1209+
MCRegister Reg = I.getReg();
1210+
if (NeedsFrameRecordPop && (Reg == FPReg.asMCReg() || Reg == ARM::LR))
12111211
FrameRecord.insert(Reg);
12121212
else
12131213
SpilledGPRs.insert(Reg);

‎llvm/lib/Target/AVR/AVRFrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -254,7 +254,7 @@ bool AVRFrameLowering::spillCalleeSavedRegisters(
254254
AVRMachineFunctionInfo *AVRFI = MF.getInfo<AVRMachineFunctionInfo>();
255255

256256
for (const CalleeSavedInfo &I : llvm::reverse(CSI)) {
257-
Register Reg = I.getReg();
257+
MCRegister Reg = I.getReg();
258258
bool IsNotLiveIn = !MBB.isLiveIn(Reg);
259259

260260
// Check if Reg is a sub register of a 16-bit livein register, and then
@@ -302,7 +302,7 @@ bool AVRFrameLowering::restoreCalleeSavedRegisters(
302302
const TargetInstrInfo &TII = *STI.getInstrInfo();
303303

304304
for (const CalleeSavedInfo &CCSI : CSI) {
305-
Register Reg = CCSI.getReg();
305+
MCRegister Reg = CCSI.getReg();
306306

307307
assert(TRI->getRegSizeInBits(*TRI->getMinimalPhysRegClass(Reg)) == 8 &&
308308
"Invalid register size");

‎llvm/lib/Target/CSKY/CSKYFrameLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ void CSKYFrameLowering::emitPrologue(MachineFunction &MF,
135135
// directives.
136136
for (const auto &Entry : CSI) {
137137
int64_t Offset = MFI.getObjectOffset(Entry.getFrameIdx());
138-
Register Reg = Entry.getReg();
138+
MCRegister Reg = Entry.getReg();
139139

140140
unsigned Num = TRI->getRegSizeInBits(Reg, MRI) / 32;
141141
for (unsigned i = 0; i < Num; i++) {
@@ -474,7 +474,7 @@ bool CSKYFrameLowering::spillCalleeSavedRegisters(
474474

475475
for (auto &CS : CSI) {
476476
// Insert the spill to the stack frame.
477-
Register Reg = CS.getReg();
477+
MCRegister Reg = CS.getReg();
478478
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
479479
TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), RC, TRI,
480480
Register());
@@ -496,7 +496,7 @@ bool CSKYFrameLowering::restoreCalleeSavedRegisters(
496496
DL = MI->getDebugLoc();
497497

498498
for (auto &CS : reverse(CSI)) {
499-
Register Reg = CS.getReg();
499+
MCRegister Reg = CS.getReg();
500500
const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
501501
TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI,
502502
Register());

‎llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1409,7 +1409,7 @@ bool HexagonFrameLowering::insertCSRSpillsInBlock(MachineBasicBlock &MBB,
14091409
}
14101410

14111411
for (const CalleeSavedInfo &I : CSI) {
1412-
Register Reg = I.getReg();
1412+
MCRegister Reg = I.getReg();
14131413
// Add live in registers. We treat eh_return callee saved register r0 - r3
14141414
// specially. They are not really callee saved registers as they are not
14151415
// supposed to be killed.
@@ -1478,7 +1478,7 @@ bool HexagonFrameLowering::insertCSRRestoresInBlock(MachineBasicBlock &MBB,
14781478
}
14791479

14801480
for (const CalleeSavedInfo &I : CSI) {
1481-
Register Reg = I.getReg();
1481+
MCRegister Reg = I.getReg();
14821482
const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
14831483
int FI = I.getFrameIdx();
14841484
HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI, Register());
@@ -1512,7 +1512,7 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
15121512
return;
15131513

15141514
// Set the physical aligned-stack base address register.
1515-
Register AP = 0;
1515+
MCRegister AP;
15161516
if (const MachineInstr *AI = getAlignaInstr(MF))
15171517
AP = AI->getOperand(0).getReg();
15181518
auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
@@ -2588,7 +2588,7 @@ bool HexagonFrameLowering::shouldInlineCSR(const MachineFunction &MF,
25882588
// a contiguous block starting from D8.
25892589
BitVector Regs(Hexagon::NUM_TARGET_REGS);
25902590
for (const CalleeSavedInfo &I : CSI) {
2591-
Register R = I.getReg();
2591+
MCRegister R = I.getReg();
25922592
if (!Hexagon::DoubleRegsRegClass.contains(R))
25932593
return true;
25942594
Regs[R] = true;

‎llvm/lib/Target/LoongArch/LoongArchFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -438,7 +438,7 @@ bool LoongArchFrameLowering::spillCalleeSavedRegisters(
438438

439439
// Insert the spill to the stack frame.
440440
for (auto &CS : CSI) {
441-
Register Reg = CS.getReg();
441+
MCRegister Reg = CS.getReg();
442442
// If the register is RA and the return address is taken by method
443443
// LoongArchTargetLowering::lowerRETURNADDR, don't set kill flag.
444444
bool IsKill =

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