|
1 |
| -# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5 |
| 1 | +# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5 |
2 | 2 | # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK,CHECK-TRUE16 %s
|
3 | 3 | # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK,CHECK-TRUE16 %s
|
4 | 4 | # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble %s | FileCheck -strict-whitespace -check-prefixes=CHECK,CHECK-FAKE16 %s
|
|
78 | 78 | # CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l wait_exp:0
|
79 | 79 | # CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:0
|
80 | 80 |
|
81 |
| -0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x04 |
82 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l wait_exp:0 |
83 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:0 |
84 |
| - |
85 | 81 | 0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x24
|
86 | 82 | # CHECK-TRUE16: v_interp_p10_f16_f32 v0, -v1.l, v2, v3.l wait_exp:0
|
87 | 83 | # CHECK-FAKE16: v_interp_p10_f16_f32 v0, -v1, v2, v3 wait_exp:0
|
|
130 | 126 | # CHECK-TRUE16: v_interp_p10_f16_f32 v0, -v1.h, -v2, -v3.h clamp op_sel:[1,0,1,0] wait_exp:5
|
131 | 127 | # CHECK-FAKE16: v_interp_p10_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,1,0] wait_exp:5
|
132 | 128 |
|
133 |
| -0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x24 |
134 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, -v1.l, v2, v3.l wait_exp:0 |
135 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, -v1, v2, v3 wait_exp:0 |
136 |
| - |
137 |
| -0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x44 |
138 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, -v2, v3.l wait_exp:0 |
139 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, -v2, v3 wait_exp:0 |
140 |
| - |
141 |
| -0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x84 |
142 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, -v3.l wait_exp:0 |
143 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, -v3 wait_exp:0 |
144 |
| - |
145 |
| -0x00,0x80,0x02,0xcd,0x01,0x05,0x0e,0x04 |
146 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l clamp wait_exp:0 |
147 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 clamp wait_exp:0 |
148 |
| - |
149 |
| -0x00,0x01,0x02,0xcd,0x01,0x05,0x0e,0x04 |
150 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l wait_exp:1 |
151 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:1 |
152 |
| - |
153 |
| -0x00,0x07,0x02,0xcd,0x01,0x05,0x0e,0x04 |
154 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l wait_exp:7 |
155 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 wait_exp:7 |
156 |
| - |
157 |
| -0x00,0x08,0x02,0xcd,0x01,0x05,0x0e,0x04 |
158 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.h, v2, v3.l op_sel:[1,0,0,0] wait_exp:0 |
159 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0 |
160 |
| - |
161 | 129 | 0x00,0x10,0x02,0xcd,0x01,0x05,0x0e,0x04
|
162 | 130 | # CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l op_sel:[0,1,0,0] wait_exp:0
|
163 | 131 | # CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
|
164 | 132 |
|
165 |
| -0x00,0x20,0x02,0xcd,0x01,0x05,0x0e,0x04 |
166 |
| -# CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, v3.h op_sel:[0,0,1,0] wait_exp:0 |
167 |
| -# CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0 |
168 |
| - |
169 | 133 | 0x00,0x40,0x02,0xcd,0x01,0x05,0x0e,0x04
|
170 | 134 | # CHECK-TRUE16: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l op_sel:[0,0,0,1] wait_exp:0
|
171 | 135 | # CHECK-FAKE16: v_interp_p10_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
|
|
190 | 154 | # CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:0
|
191 | 155 | # CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:0
|
192 | 156 |
|
193 |
| -0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x04 |
194 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:0 |
195 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:0 |
196 |
| - |
197 | 157 | 0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x24
|
198 | 158 | # CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, -v1.l, v2, v3 wait_exp:0
|
199 | 159 | # CHECK-FAKE16: v_interp_p2_f16_f32 v0, -v1, v2, v3 wait_exp:0
|
|
238 | 198 | # CHECK-TRUE16: v_interp_p2_f16_f32 v0.h, -v1.h, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
|
239 | 199 | # CHECK-FAKE16: v_interp_p2_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
|
240 | 200 |
|
241 |
| -0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x24 |
242 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, -v1.l, v2, v3 wait_exp:0 |
243 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, -v1, v2, v3 wait_exp:0 |
244 |
| - |
245 |
| -0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x44 |
246 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, -v2, v3 wait_exp:0 |
247 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, -v2, v3 wait_exp:0 |
248 |
| - |
249 |
| -0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x84 |
250 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, v2, -v3 wait_exp:0 |
251 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, -v3 wait_exp:0 |
252 |
| - |
253 |
| -0x00,0x80,0x03,0xcd,0x01,0x05,0x0e,0x04 |
254 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 clamp wait_exp:0 |
255 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp wait_exp:0 |
256 |
| - |
257 |
| -0x00,0x01,0x03,0xcd,0x01,0x05,0x0e,0x04 |
258 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:1 |
259 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:1 |
260 |
| - |
261 |
| -0x00,0x07,0x03,0xcd,0x01,0x05,0x0e,0x04 |
262 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7 |
263 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 wait_exp:7 |
264 |
| - |
265 |
| -0x00,0x08,0x03,0xcd,0x01,0x05,0x0e,0x04 |
266 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.h, v2, v3 op_sel:[1,0,0,0] wait_exp:0 |
267 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0 |
268 |
| - |
269 | 201 | 0x00,0x10,0x03,0xcd,0x01,0x05,0x0e,0x04
|
270 | 202 | # CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 op_sel:[0,1,0,0] wait_exp:0
|
271 | 203 | # CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
|
|
274 | 206 | # CHECK-TRUE16: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 op_sel:[0,0,1,0] wait_exp:0
|
275 | 207 | # CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
|
276 | 208 |
|
277 |
| -0x00,0x40,0x03,0xcd,0x01,0x05,0x0e,0x04 |
278 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.h, v1.l, v2, v3 op_sel:[0,0,0,1] wait_exp:0 |
279 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0 |
280 |
| - |
281 | 209 | 0x00,0x78,0x03,0xcd,0x01,0x05,0x0e,0x04
|
282 | 210 | # CHECK-TRUE16: v_interp_p2_f16_f32 v0.h, v1.h, v2, v3 op_sel:[1,1,1,1] wait_exp:0
|
283 | 211 | # CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
|
284 | 212 |
|
285 |
| -0x00,0x4d,0x03,0xcd,0x01,0x05,0x0e,0x04 |
286 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.h, v1.h, v2, v3 op_sel:[1,0,0,1] wait_exp:5 |
287 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5 |
288 |
| - |
289 |
| -0x00,0xcd,0x03,0xcd,0x01,0x05,0x0e,0x04 |
290 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.h, v1.h, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5 |
291 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5 |
292 |
| - |
293 |
| -0x00,0xcd,0x03,0xcd,0x01,0x05,0x0e,0xe4 |
294 |
| -# CHECK-TRUE16: v_interp_p2_f16_f32 v0.h, -v1.h, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5 |
295 |
| -# CHECK-FAKE16: v_interp_p2_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5 |
296 |
| - |
297 |
| -0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x04 |
298 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l wait_exp:0 |
299 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0 |
300 |
| - |
301 | 213 | 0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x04
|
302 | 214 | # CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l wait_exp:0
|
303 | 215 | # CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0
|
|
342 | 254 | # CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, -v1.h, -v2, -v3.h clamp op_sel:[1,0,1,0] wait_exp:5
|
343 | 255 | # CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,1,0] wait_exp:5
|
344 | 256 |
|
345 |
| -0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x24 |
346 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, -v1.l, v2, v3.l wait_exp:0 |
347 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0 |
348 |
| - |
349 |
| -0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x44 |
350 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, -v2, v3.l wait_exp:0 |
351 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0 |
352 |
| - |
353 |
| -0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x84 |
354 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, -v3.l wait_exp:0 |
355 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0 |
356 |
| - |
357 |
| -0x00,0x80,0x04,0xcd,0x01,0x05,0x0e,0x04 |
358 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l clamp wait_exp:0 |
359 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0 |
360 |
| - |
361 |
| -0x00,0x01,0x04,0xcd,0x01,0x05,0x0e,0x04 |
362 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l wait_exp:1 |
363 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1 |
364 |
| - |
365 |
| -0x00,0x07,0x04,0xcd,0x01,0x05,0x0e,0x04 |
366 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l wait_exp:7 |
367 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7 |
368 |
| - |
369 |
| -0x00,0x08,0x04,0xcd,0x01,0x05,0x0e,0x04 |
370 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.h, v2, v3.l op_sel:[1,0,0,0] wait_exp:0 |
371 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0 |
372 |
| - |
373 | 257 | 0x00,0x10,0x04,0xcd,0x01,0x05,0x0e,0x04
|
374 | 258 | # CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l op_sel:[0,1,0,0] wait_exp:0
|
375 | 259 | # CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
|
376 | 260 |
|
377 |
| -0x00,0x20,0x04,0xcd,0x01,0x05,0x0e,0x04 |
378 |
| -# CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.h op_sel:[0,0,1,0] wait_exp:0 |
379 |
| -# CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0 |
380 |
| - |
381 | 261 | 0x00,0x40,0x04,0xcd,0x01,0x05,0x0e,0x04
|
382 | 262 | # CHECK-TRUE16: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l op_sel:[0,0,0,1] wait_exp:0
|
383 | 263 | # CHECK-FAKE16: v_interp_p10_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0
|
|
402 | 282 | # CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:0
|
403 | 283 | # CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0
|
404 | 284 |
|
405 |
| -0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x04 |
406 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:0 |
407 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:0 |
408 |
| - |
409 | 285 | 0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x24
|
410 | 286 | # CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, -v1.l, v2, v3 wait_exp:0
|
411 | 287 | # CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0
|
|
450 | 326 | # CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.h, -v1.h, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
|
451 | 327 | # CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5
|
452 | 328 |
|
453 |
| -0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x24 |
454 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, -v1.l, v2, v3 wait_exp:0 |
455 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, -v1, v2, v3 wait_exp:0 |
456 |
| - |
457 |
| -0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x44 |
458 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, -v2, v3 wait_exp:0 |
459 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, -v2, v3 wait_exp:0 |
460 |
| - |
461 |
| -0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x84 |
462 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, -v3 wait_exp:0 |
463 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, -v3 wait_exp:0 |
464 |
| - |
465 |
| -0x00,0x80,0x05,0xcd,0x01,0x05,0x0e,0x04 |
466 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 clamp wait_exp:0 |
467 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp wait_exp:0 |
468 |
| - |
469 |
| -0x00,0x01,0x05,0xcd,0x01,0x05,0x0e,0x04 |
470 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:1 |
471 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:1 |
472 |
| - |
473 |
| -0x00,0x07,0x05,0xcd,0x01,0x05,0x0e,0x04 |
474 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7 |
475 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 wait_exp:7 |
476 |
| - |
477 |
| -0x00,0x08,0x05,0xcd,0x01,0x05,0x0e,0x04 |
478 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.h, v2, v3 op_sel:[1,0,0,0] wait_exp:0 |
479 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,0] wait_exp:0 |
480 |
| - |
481 | 329 | 0x00,0x10,0x05,0xcd,0x01,0x05,0x0e,0x04
|
482 | 330 | # CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 op_sel:[0,1,0,0] wait_exp:0
|
483 | 331 | # CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,1,0,0] wait_exp:0
|
|
486 | 334 | # CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 op_sel:[0,0,1,0] wait_exp:0
|
487 | 335 | # CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,1,0] wait_exp:0
|
488 | 336 |
|
489 |
| -0x00,0x40,0x05,0xcd,0x01,0x05,0x0e,0x04 |
490 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.h, v1.l, v2, v3 op_sel:[0,0,0,1] wait_exp:0 |
491 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[0,0,0,1] wait_exp:0 |
492 |
| - |
493 | 337 | 0x00,0x78,0x05,0xcd,0x01,0x05,0x0e,0x04
|
494 | 338 | # CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v3 op_sel:[1,1,1,1] wait_exp:0
|
495 | 339 | # CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,1,1,1] wait_exp:0
|
496 |
| - |
497 |
| -0x00,0x4d,0x05,0xcd,0x01,0x05,0x0e,0x04 |
498 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v3 op_sel:[1,0,0,1] wait_exp:5 |
499 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 op_sel:[1,0,0,1] wait_exp:5 |
500 |
| - |
501 |
| -0x00,0xcd,0x05,0xcd,0x01,0x05,0x0e,0x04 |
502 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.h, v1.h, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5 |
503 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, v1, v2, v3 clamp op_sel:[1,0,0,1] wait_exp:5 |
504 |
| - |
505 |
| -0x00,0xcd,0x05,0xcd,0x01,0x05,0x0e,0xe4 |
506 |
| -# CHECK-TRUE16: v_interp_p2_rtz_f16_f32 v0.h, -v1.h, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5 |
507 |
| -# CHECK-FAKE16: v_interp_p2_rtz_f16_f32 v0, -v1, -v2, -v3 clamp op_sel:[1,0,0,1] wait_exp:5 |
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