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espindolaespindola
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Don't print (PLT) on arm.
The R_ARM_PLT32 relocation is deprecated and is not produced by MC. This means that the code being deleted is dead from the .o point of view and was making the .s more confusing. llvm-svn: 272909
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10 files changed

+29
-57
lines changed

10 files changed

+29
-57
lines changed

‎llvm/lib/Target/ARM/ARMAsmPrinter.cpp

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -212,8 +212,6 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
212212
GetARMGVSymbol(GV, TF)->print(O, MAI);
213213

214214
printOffset(MO.getOffset(), O);
215-
if (TF == ARMII::MO_PLT)
216-
O << "(PLT)";
217215
break;
218216
}
219217
case MachineOperand::MO_ConstantPoolIndex:

‎llvm/lib/Target/ARM/ARMFastISel.cpp

Lines changed: 2 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2430,22 +2430,15 @@ bool ARMFastISel::SelectCall(const Instruction *I,
24302430
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
24312431
DbgLoc, TII.get(CallOpc));
24322432

2433-
unsigned char OpFlags = 0;
2434-
2435-
// Add MO_PLT for global address or external symbol in the PIC relocation
2436-
// model.
2437-
if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2438-
OpFlags = ARMII::MO_PLT;
2439-
24402433
// ARM calls don't take a predicate, but tBL / tBLX do.
24412434
if(isThumb2)
24422435
AddDefaultPred(MIB);
24432436
if (UseReg)
24442437
MIB.addReg(CalleeReg);
24452438
else if (!IntrMemName)
2446-
MIB.addGlobalAddress(GV, 0, OpFlags);
2439+
MIB.addGlobalAddress(GV, 0, 0);
24472440
else
2448-
MIB.addExternalSymbol(IntrMemName, OpFlags);
2441+
MIB.addExternalSymbol(IntrMemName, 0);
24492442

24502443
// Add implicit physical register uses to the call.
24512444
for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1878,12 +1878,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
18781878
MachinePointerInfo::getGOT(DAG.getMachineFunction()),
18791879
false, false, false, 0);
18801880
} else {
1881-
// On ELF targets for PIC code, direct calls should go through the PLT
1882-
unsigned OpFlags = 0;
1883-
if (Subtarget->isTargetELF() &&
1884-
getTargetMachine().getRelocationModel() == Reloc::PIC_)
1885-
OpFlags = ARMII::MO_PLT;
1886-
Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, OpFlags);
1881+
Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
18871882
}
18881883
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
18891884
isDirect = true;
@@ -1903,12 +1898,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
19031898
SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
19041899
Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
19051900
} else {
1906-
unsigned OpFlags = 0;
1907-
// On ELF targets for PIC code, direct calls should go through the PLT
1908-
if (Subtarget->isTargetELF() &&
1909-
getTargetMachine().getRelocationModel() == Reloc::PIC_)
1910-
OpFlags = ARMII::MO_PLT;
1911-
Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, OpFlags);
1901+
Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
19121902
}
19131903
}
19141904

‎llvm/lib/Target/ARM/ARMMCInstLower.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -49,11 +49,6 @@ MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
4949
}
5050
break;
5151
}
52-
53-
case ARMII::MO_PLT:
54-
Expr = MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_PLT,
55-
OutContext);
56-
break;
5752
}
5853

5954
if (!MO.isJTI() && MO.getOffset())

‎llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -289,10 +289,6 @@ namespace ARMII {
289289
/// higher 16 bit of the address. Used only via movt instruction.
290290
MO_HI16 = 0x2,
291291

292-
/// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
293-
/// call operand.
294-
MO_PLT = 0x3,
295-
296292
/// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
297293
/// just that part of the flag set.
298294
MO_OPTION_MASK = 0x1f,

‎llvm/test/CodeGen/ARM/call-tc.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ declare void @g(i32, i32, i32, i32)
1212

1313
define void @t1() {
1414
; CHECKELF-LABEL: t1:
15-
; CHECKELF: bl g(PLT)
15+
; CHECKELF: bl g
1616
call void @g( i32 1, i32 2, i32 3, i32 4 )
1717
ret void
1818
}
@@ -33,7 +33,7 @@ define void @t3() {
3333
; CHECKV6-LABEL: t3:
3434
; CHECKV6: b _t2
3535
; CHECKELF-LABEL: t3:
36-
; CHECKELF: b t2(PLT)
36+
; CHECKELF: b t2
3737
; CHECKT2D-LABEL: t3:
3838
; CHECKT2D: b.w _t2
3939

@@ -47,7 +47,7 @@ entry:
4747
; CHECKV6-LABEL: t4:
4848
; CHECKV6: b _sin
4949
; CHECKELF-LABEL: t4:
50-
; CHECKELF: b sin(PLT)
50+
; CHECKELF: b sin
5151
%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
5252
ret double %0
5353
}
@@ -57,7 +57,7 @@ entry:
5757
; CHECKV6-LABEL: t5:
5858
; CHECKV6: b _sinf
5959
; CHECKELF-LABEL: t5:
60-
; CHECKELF: b sinf(PLT)
60+
; CHECKELF: b sinf
6161
%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
6262
ret float %0
6363
}
@@ -71,7 +71,7 @@ entry:
7171
; CHECKV6-LABEL: t6:
7272
; CHECKV6: b ___divsi3
7373
; CHECKELF-LABEL: t6:
74-
; CHECKELF: b __aeabi_idiv(PLT)
74+
; CHECKELF: b __aeabi_idiv
7575
%0 = sdiv i32 %a, %b
7676
ret i32 %0
7777
}

‎llvm/test/CodeGen/ARM/call.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
declare void @g(i32, i32, i32, i32)
1313

1414
define void @f() {
15-
; CHECKELF: PLT
15+
; CHECKELF: bl g
1616
call void @g( i32 1, i32 2, i32 3, i32 4 )
1717
ret void
1818
}

‎llvm/test/CodeGen/ARM/emutls.ll

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ define i32 @my_get_xyz() {
1111
; ARM32-LABEL: my_get_xyz:
1212
; ARM32: ldr r0,
1313
; ARM32: ldr r0, [pc, r0]
14-
; ARM32-NEXT: bl my_emutls_get_address(PLT)
14+
; ARM32-NEXT: bl my_emutls_get_address
1515
; ARM32-NEXT: ldr r0, [r0]
1616
; ARM32: .long my_emutls_v_xyz(GOT_PREL)
1717

@@ -34,7 +34,7 @@ define i32 @f1() {
3434
; ARM32-LABEL: f1:
3535
; ARM32: ldr r0,
3636
; ARM32: ldr r0, [pc, r0]
37-
; ARM32-NEXT: bl __emutls_get_address(PLT)
37+
; ARM32-NEXT: bl __emutls_get_address
3838
; ARM32-NEXT: ldr r0, [r0]
3939
; ARM32: .long __emutls_v.i1(GOT_PREL)
4040

@@ -47,7 +47,7 @@ define i32* @f2() {
4747
; ARM32-LABEL: f2:
4848
; ARM32: ldr r0,
4949
; ARM32: ldr r0, [pc, r0]
50-
; ARM32-NEXT: bl __emutls_get_address(PLT)
50+
; ARM32-NEXT: bl __emutls_get_address
5151
; ARM32-NEXT: pop
5252
; ARM32: .long __emutls_v.i1(GOT_PREL)
5353

@@ -59,7 +59,7 @@ define i32 @f3() nounwind {
5959
; ARM32-LABEL: f3:
6060
; ARM32: ldr r0,
6161
; ARM32: ldr r0, [pc, r0]
62-
; ARM32-NEXT: bl __emutls_get_address(PLT)
62+
; ARM32-NEXT: bl __emutls_get_address
6363
; ARM32-NEXT: ldr r0, [r0]
6464
; ARM32: .long __emutls_v.i2(GOT_PREL)
6565

@@ -72,7 +72,7 @@ define i32* @f4() {
7272
; ARM32-LABEL: f4:
7373
; ARM32: ldr r0,
7474
; ARM32: ldr r0, [pc, r0]
75-
; ARM32-NEXT: bl __emutls_get_address(PLT)
75+
; ARM32-NEXT: bl __emutls_get_address
7676
; ARM32-NEXT: pop
7777
; ARM32: .long __emutls_v.i2(GOT_PREL)
7878

@@ -84,7 +84,7 @@ define i32 @f5() nounwind {
8484
; ARM32-LABEL: f5:
8585
; ARM32: ldr r0,
8686
; ARM32: add r0, pc, r0
87-
; ARM32-NEXT: bl __emutls_get_address(PLT)
87+
; ARM32-NEXT: bl __emutls_get_address
8888
; ARM32-NEXT: ldr r0, [r0]
8989
; ARM32: .long __emutls_v.i3-
9090

@@ -97,7 +97,7 @@ define i32* @f6() {
9797
; ARM32-LABEL: f6:
9898
; ARM32: ldr r0,
9999
; ARM32: add r0, pc, r0
100-
; ARM32-NEXT: bl __emutls_get_address(PLT)
100+
; ARM32-NEXT: bl __emutls_get_address
101101
; ARM32-NEXT: pop
102102
; ARM32: .long __emutls_v.i3-
103103

@@ -109,7 +109,7 @@ define i32 @f7() {
109109
; ARM32-LABEL: f7:
110110
; ARM32: ldr r0,
111111
; ARM32: add r0, pc, r0
112-
; ARM32-NEXT: bl __emutls_get_address(PLT)
112+
; ARM32-NEXT: bl __emutls_get_address
113113
; ARM32-NEXT: ldr r0, [r0]
114114
; ARM32: .long __emutls_v.i4-(.LPC
115115

@@ -122,7 +122,7 @@ define i32* @f8() {
122122
; ARM32-LABEL: f8:
123123
; ARM32: ldr r0,
124124
; ARM32: add r0, pc, r0
125-
; ARM32-NEXT: bl __emutls_get_address(PLT)
125+
; ARM32-NEXT: bl __emutls_get_address
126126
; ARM32-NEXT: pop
127127
; ARM32: .long __emutls_v.i4-(.LPC
128128

@@ -134,7 +134,7 @@ define i32 @f9() {
134134
; ARM32-LABEL: f9:
135135
; ARM32: ldr r0,
136136
; ARM32: add r0, pc, r0
137-
; ARM32-NEXT: bl __emutls_get_address(PLT)
137+
; ARM32-NEXT: bl __emutls_get_address
138138
; ARM32-NEXT: ldr r0, [r0]
139139

140140
entry:
@@ -146,7 +146,7 @@ define i32* @f10() {
146146
; ARM32-LABEL: f10:
147147
; ARM32: ldr r0,
148148
; ARM32: add r0, pc, r0
149-
; ARM32-NEXT: bl __emutls_get_address(PLT)
149+
; ARM32-NEXT: bl __emutls_get_address
150150
; ARM32-NEXT: pop
151151

152152
entry:
@@ -157,7 +157,7 @@ define i16 @f11() {
157157
; ARM32-LABEL: f11:
158158
; ARM32: ldr r0,
159159
; ARM32: ldr r0, [pc, r0]
160-
; ARM32-NEXT: bl __emutls_get_address(PLT)
160+
; ARM32-NEXT: bl __emutls_get_address
161161
; ARM32-NEXT: ldrh r0, [r0]
162162

163163
entry:
@@ -169,7 +169,7 @@ define i32 @f12() {
169169
; ARM32-LABEL: f12:
170170
; ARM32: ldr r0,
171171
; ARM32: ldr r0, [pc, r0]
172-
; ARM32-NEXT: bl __emutls_get_address(PLT)
172+
; ARM32-NEXT: bl __emutls_get_address
173173
; ARM32-NEXT: ldrsh r0, [r0]
174174

175175
entry:
@@ -182,7 +182,7 @@ define i8 @f13() {
182182
; ARM32-LABEL: f13:
183183
; ARM32: ldr r0,
184184
; ARM32: ldr r0, [pc, r0]
185-
; ARM32-NEXT: bl __emutls_get_address(PLT)
185+
; ARM32-NEXT: bl __emutls_get_address
186186
; ARM32-NEXT: ldrb r0, [r0]
187187
; ARM32-NEXT: pop
188188

@@ -195,7 +195,7 @@ define i32 @f14() {
195195
; ARM32-LABEL: f14:
196196
; ARM32: ldr r0,
197197
; ARM32: ldr r0, [pc, r0]
198-
; ARM32-NEXT: bl __emutls_get_address(PLT)
198+
; ARM32-NEXT: bl __emutls_get_address
199199
; ARM32-NEXT: ldrsb r0, [r0]
200200
; ARM32-NEXT: pop
201201

‎llvm/test/CodeGen/ARM/pic.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,10 @@ define void @test() {
1111
entry:
1212

1313
%0 = call i32 @get()
14-
; CHECK: bl get(PLT)
14+
; CHECK: bl get
1515

1616
call void @put(i32 %0)
17-
; CHECK: bl put(PLT)
17+
; CHECK: bl put
1818

1919
ret void
2020
}

‎llvm/test/CodeGen/Thumb2/tls2.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ entry:
1111
; CHECK-NOT-PIC: i(GOTTPOFF)
1212

1313
; CHECK-PIC-LABEL: f:
14-
; CHECK-PIC: bl __tls_get_addr(PLT)
14+
; CHECK-PIC: bl __tls_get_addr
1515
%tmp1 = load i32, i32* @i ; <i32> [#uses=1]
1616
ret i32 %tmp1
1717
}
@@ -24,6 +24,6 @@ entry:
2424
; CHECK-NOT-PIC: i(GOTTPOFF)
2525

2626
; CHECK-PIC-LABEL: g:
27-
; CHECK-PIC: bl __tls_get_addr(PLT)
27+
; CHECK-PIC: bl __tls_get_addr
2828
ret i32* @i
2929
}

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