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[AMDGPU] Add s_wait_xcnt gfx1250 instruction (#145086)
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llvm/lib/Target/AMDGPU/AMDGPU.td

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@@ -1112,6 +1112,12 @@ def FeaturePointSampleAccel : SubtargetFeature<"point-sample-accel",
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"Has point sample acceleration feature"
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>;
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def FeatureWaitXcnt : SubtargetFeature<"wait-xcnt",
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"HasWaitXcnt",
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"true",
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"Has s_wait_xcnt instruction"
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>;
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//===------------------------------------------------------------===//
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// Subtarget Features (options and debugging)
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//===------------------------------------------------------------===//
@@ -1927,6 +1933,7 @@ def FeatureISAVersion12_50 : FeatureSet<
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FeatureAshrPkInsts,
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FeatureSupportsSRAMECC,
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FeatureMaxHardClauseLength63,
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FeatureWaitXcnt,
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FeatureAtomicFMinFMaxF64GlobalInsts,
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FeatureAtomicFMinFMaxF64FlatInsts,
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FeatureFlatBufferGlobalAtomicFaddF64Inst,
@@ -2591,6 +2598,9 @@ def HasPrngInst : Predicate<"Subtarget->hasPrngInst()">,
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def HasBVHDualAndBVH8Insts : Predicate<"Subtarget->hasBVHDualAndBVH8Insts()">,
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AssemblerPredicate<(all_of FeatureBVHDualAndBVH8Insts)>;
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def HasWaitXcnt : Predicate<"Subtarget->hasWaitXcnt()">,
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AssemblerPredicate<(all_of FeatureWaitXcnt)>;
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def HasFP8ConversionScaleInsts : Predicate<"Subtarget->hasFP8ConversionScaleInsts()">,
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AssemblerPredicate<(all_of FeatureFP8ConversionScaleInsts)>;
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llvm/lib/Target/AMDGPU/GCNSubtarget.h

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@@ -202,6 +202,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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bool HasNoSdstCMPX = false;
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bool HasVscnt = false;
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bool HasWaitXcnt = false;
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bool HasGetWaveIdInst = false;
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bool HasSMemTimeInst = false;
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bool HasShaderCyclesRegister = false;
@@ -1368,6 +1369,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
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return HasMinimum3Maximum3PKF16;
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}
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/// \returns true if the target has s_wait_xcnt insertion. Supported for
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/// GFX1250.
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bool hasWaitXCnt() const { return HasWaitXcnt; }
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bool hasPointSampleAccel() const { return HasPointSampleAccel; }
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/// \returns The maximum number of instructions that can be enclosed in an

llvm/lib/Target/AMDGPU/SOPInstructions.td

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@@ -1751,6 +1751,11 @@ let OtherPredicates = [HasExportInsts] in
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[(int_amdgcn_s_wait_kmcnt timm:$simm16)]>;
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} // End SubtargetPredicate = isGFX12Plus, hasSideEffects = 1
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let SubtargetPredicate = HasWaitXcnt, hasSideEffects = 1 in {
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def S_WAIT_XCNT :
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SOPP_Pseudo<"s_wait_xcnt", (ins s16imm:$simm16), "$simm16">;
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} // End SubtargetPredicate = hasWaitXcnt, hasSideEffects = 1
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//===----------------------------------------------------------------------===//
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// SOP1 Patterns
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//===----------------------------------------------------------------------===//
@@ -2560,6 +2565,11 @@ defm S_WAIT_KMCNT : SOPP_Real_32_gfx12<0x047>;
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defm S_WAIT_LOADCNT_DSCNT : SOPP_Real_32_gfx12<0x048>;
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defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>;
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//===----------------------------------------------------------------------===//
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// SOPP - GFX1250 only.
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//===----------------------------------------------------------------------===//
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defm S_WAIT_XCNT : SOPP_Real_32_gfx12<0x045>;
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//===----------------------------------------------------------------------===//
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// SOPP - GFX11, GFX12.
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//===----------------------------------------------------------------------===//
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// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s
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// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s 2>&1 | FileCheck --check-prefixes=GFX12-ERR --implicit-check-not=error: -strict-whitespace %s
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s_wait_xcnt 0x0
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// GFX1250: [0x00,0x00,0xc5,0xbf]
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// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
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s_wait_xcnt 0x7
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// GFX1250: [0x07,0x00,0xc5,0xbf]
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// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
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s_wait_xcnt 0xf
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// GFX1250: [0x0f,0x00,0xc5,0xbf]
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// GFX12-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
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# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX1250 %s
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# GFX1250: s_wait_xcnt 0x0 ; encoding: [0x00,0x00,0xc5,0xbf]
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0x00,0x00,0xc5,0xbf
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# GFX1250: s_wait_xcnt 0x7 ; encoding: [0x07,0x00,0xc5,0xbf]
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0x07,0x00,0xc5,0xbf
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# GFX1250: s_wait_xcnt 0xf ; encoding: [0x0f,0x00,0xc5,0xbf]
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0x0f,0x00,0xc5,0xbf

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