[Clang][SME2] Add single and multi min and max builtins (#71688)

Adds the following SME2 builtins:

    svmin_single_(s8|s16|s32|s64)_x(2|4)
    svmin_single_(u8|u16|u32|u64)_x(2|4)
    svmin_single_(f16|f32|f64)_x(2|4)
    svmin_(s8|s16|s32|s64)_x(2|4)
    svmin_(u8|u16|u32|u64)_x(2|4)
    svmin_(f16|f32|f64)_x(2|4)
    svmax_single_(s8|s16|s32|s64)_x(2|4)
    svmax_single_(u8|u16|u32|u64)_x(2|4)
    svmax_single_(f16|f32|f64)_x(2|4)
    svmax_(s8|s16|s32|s64)_x(2|4)
    svmax_(u8|u16|u32|u64)_x(2|4)
    svmax_(f16|f32|f64)_x(2|4)

See
[https://github.com/ARM-software/acle/pull/217](https://github.com/ARM-software/acle/pull/217)

Patch by: Kerry McLaughlin <[email protected]>

Author: SamTebbs33

clang/include/clang/Basic/arm_sve.td

@@ -1987,6 +1987,26 @@ defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
 // SME intrinsics which operate only on vectors and do not require ZA should be added here,
 // as they could possibly become SVE instructions in the future.
 
+multiclass MinMaxIntr<string i, string zm, string mul, string t> {
+  def SVS # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "csil",     MergeNone, "aarch64_sve_s" # i # zm # "_" # mul, [IsStreaming], []>;
+  def SVU # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "UcUsUiUl", MergeNone, "aarch64_sve_u" # i # zm # "_" # mul, [IsStreaming], []>;
+  def SVF # NAME : SInst<"sv" # i # "[" # zm # "_{d}_" # mul # "]", t, "hfd",      MergeNone, "aarch64_sve_f" # i # zm # "_" # mul, [IsStreaming], []>;
+}
+
+let TargetGuard = "sme2" in {
+// == SMAX / UMAX / FMAX ==
+  defm MAX_SINGLE_X2 : MinMaxIntr<"max", "_single", "x2", "22d">;
+  defm MAX_MULTI_X2  : MinMaxIntr<"max", "",        "x2", "222">;
+  defm MAX_SINGLE_X4 : MinMaxIntr<"max", "_single", "x4", "44d">;
+  defm MAX_MULTI_X4  : MinMaxIntr<"max", "",        "x4", "444">;
+
+// == SMIN / UMIN / FMIN ==
+  defm MIN_SINGLE_X2 : MinMaxIntr<"min", "_single", "x2", "22d">;
+  defm MIN_MULTI_X2  : MinMaxIntr<"min", "",        "x2", "222">;
+  defm MIN_SINGLE_X4 : MinMaxIntr<"min", "_single", "x4", "44d">;
+  defm MIN_MULTI_X4  : MinMaxIntr<"min", "",        "x4", "444">;
+}
+
 let TargetGuard = "sme2" in {
 // == ADD (vectors) ==
   def SVADD_SINGLE_X2 : SInst<"svadd[_single_{d}_x2]", "22d", "cUcsUsiUilUl", MergeNone, "aarch64_sve_add_single_x2", [IsStreaming], []>;