Skip to content

Commit b052af7

Browse files
committed
[ARM] Check for addend before the Value is adjusted
As part of the checks, in some cases the Value is changed according to if the Thumb bit is needed. This changes the value and can cause the calcuation to check the range to falsely fail. Moving the check before the Value is changed to ensure this cannot occur. Previously, tests existed that exploited the truncation of the addend into a 16bit signed value, so these tests have been updated to reflect the fact this is no longer allowed. It still tests the instruction, but the expected outcome has been updated with new values.
1 parent 6bdde34 commit b052af7

File tree

3 files changed

+18
-16
lines changed

3 files changed

+18
-16
lines changed

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -447,6 +447,16 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
447447
const MCSubtargetInfo* STI) const {
448448
unsigned Kind = Fixup.getKind();
449449

450+
// For MOVW/MOVT Instructions, the Fixup Value needs to be 16 bit aligned.
451+
// If this is not the case, we should reject compilation.
452+
if((Kind == ARM::fixup_arm_movw_lo16 || Kind == ARM::fixup_arm_movt_hi16 ||
453+
Kind == ARM::fixup_t2_movw_lo16 || Kind == ARM::fixup_t2_movt_hi16) &&
454+
(!(minIntN(16) <= static_cast<int64_t>(Value) &&
455+
static_cast<int64_t>(Value) <= maxIntN(16)))) {
456+
Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
457+
return 0;
458+
}
459+
450460
// MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
451461
// and .word relocations they put the Thumb bit into the addend if possible.
452462
// Other relocation types don't want this bit though (branches couldn't encode
@@ -473,19 +483,11 @@ unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
473483
case FK_SecRel_4:
474484
return Value;
475485
case ARM::fixup_arm_movt_hi16:
476-
if(!(minIntN(16) <= static_cast<int64_t>(Value) && static_cast<int64_t>(Value) <= maxIntN(16))) {
477-
Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
478-
return 0;
479-
}
480486
assert(STI != nullptr);
481487
if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF())
482488
Value >>= 16;
483489
[[fallthrough]];
484490
case ARM::fixup_arm_movw_lo16: {
485-
if(!(minIntN(16) <= static_cast<int64_t>(Value) && static_cast<int64_t>(Value) <= maxIntN(16))) {
486-
Ctx.reportError(Fixup.getLoc(), "Relocation Not In Range");
487-
return 0;
488-
}
489491
unsigned Hi4 = (Value & 0xF000) >> 12;
490492
unsigned Lo12 = Value & 0x0FFF;
491493
// inst{19-16} = Hi4;

llvm/test/MC/ARM/Windows/mov32t-range.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ truncation:
2121

2222
.section .rdata,"rd"
2323
.Lbuffer:
24-
.zero 65536
24+
.zero 32767
2525
.Lerange:
2626
.asciz "-erange"
2727

@@ -32,6 +32,6 @@ truncation:
3232
@ CHECK-RELOCATIONS: }
3333
@ CHECK-RELOCATIONS: ]
3434

35-
@ CHECK-ENCODING: 0: f240 0000
36-
@ CHECK-ENCODING-NEXT: 4: f2c0 0001
35+
@ CHECK-ENCODING: 0: f647 70ff
36+
@ CHECK-ENCODING-NEXT: 4: f2c0 0000
3737

llvm/test/MC/MachO/ARM/thumb2-movw-fixup.s

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
movt r2, :upper16:L1
1212
movw r12, :lower16:L2
1313
movt r12, :upper16:L2
14-
.space 70000
14+
.space 16382
1515

1616
.data
1717
L1: .long 0
@@ -30,7 +30,7 @@ L2: .long 0
3030
@ CHECK: Section: __data (2)
3131
@ CHECK: }
3232
@ CHECK: Relocation {
33-
@ CHECK: Offset: 0x1184
33+
@ CHECK: Offset: 0x4012
3434
@ CHECK: PCRel: 0
3535
@ CHECK: Length: 3
3636
@ CHECK: Type: ARM_RELOC_PAIR (1)
@@ -44,7 +44,7 @@ L2: .long 0
4444
@ CHECK: Section: __data (2)
4545
@ CHECK: }
4646
@ CHECK: Relocation {
47-
@ CHECK: Offset: 0x1
47+
@ CHECK: Offset: 0x0
4848
@ CHECK: PCRel: 0
4949
@ CHECK: Length: 2
5050
@ CHECK: Type: ARM_RELOC_PAIR (1)
@@ -58,7 +58,7 @@ L2: .long 0
5858
@ CHECK: Section: __data (2)
5959
@ CHECK: }
6060
@ CHECK: Relocation {
61-
@ CHECK: Offset: 0x1180
61+
@ CHECK: Offset: 0x400E
6262
@ CHECK: PCRel: 0
6363
@ CHECK: Length: 3
6464
@ CHECK: Type: ARM_RELOC_PAIR (1)
@@ -72,7 +72,7 @@ L2: .long 0
7272
@ CHECK: Section: __data (2)
7373
@ CHECK: }
7474
@ CHECK: Relocation {
75-
@ CHECK: Offset: 0x1
75+
@ CHECK: Offset: 0x0
7676
@ CHECK: PCRel: 0
7777
@ CHECK: Length: 2
7878
@ CHECK: Type: ARM_RELOC_PAIR (1)

0 commit comments

Comments
 (0)