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1
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2
2
; REQUIRES: asserts
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- ; RUN: opt -S < %s -p " loop-vectorize,simplifycfg" -debug-only=loop-vectorize -mattr=+sve 2>%t | FileCheck %s --check-prefixes=CHECK,CHECK-VS1
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+ ; RUN: opt -S < %s -p loop-vectorize -debug-only=loop-vectorize -mattr=+sve 2>%t | FileCheck %s --check-prefixes=CHECK,CHECK-VS1
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; RUN: cat %t | FileCheck %s --check-prefixes=DEBUG,DEBUG-VS1
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- ; RUN: opt -S < %s -p " loop-vectorize,simplifycfg" -debug-only=loop-vectorize -mcpu=neoverse-v1 -sve-tail-folding=disabled 2>%t | FileCheck %s --check-prefixes=CHECK,CHECK-VS2
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+ ; RUN: opt -S < %s -p loop-vectorize -debug-only=loop-vectorize -mcpu=neoverse-v1 -sve-tail-folding=disabled 2>%t | FileCheck %s --check-prefixes=CHECK,CHECK-VS2
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; RUN: cat %t | FileCheck %s --check-prefixes=DEBUG,DEBUG-VS2
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7
8
8
target triple = "aarch64-unknown-linux-gnu"
@@ -90,7 +90,7 @@ define void @low_vf_ic_is_better(ptr nocapture noundef %p, i32 %tc, i16 noundef
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; CHECK-VS1-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK-VS1: [[MIDDLE_BLOCK]]:
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; CHECK-VS1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
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- ; CHECK-VS1-NEXT: br i1 [[CMP_N]], label %[[WHILE_END ]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
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+ ; CHECK-VS1-NEXT: br i1 [[CMP_N]], label %[[WHILE_END_LOOPEXIT:.* ]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
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; CHECK-VS1: [[VEC_EPILOG_ITER_CHECK]]:
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; CHECK-VS1-NEXT: [[IND_END4:%.*]] = add i64 [[TMP0]], [[N_VEC]]
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; CHECK-VS1-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[TMP3]], [[N_VEC]]
@@ -123,7 +123,7 @@ define void @low_vf_ic_is_better(ptr nocapture noundef %p, i32 %tc, i16 noundef
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; CHECK-VS1-NEXT: br i1 [[TMP36]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK-VS1: [[VEC_EPILOG_MIDDLE_BLOCK]]:
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; CHECK-VS1-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC3]]
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- ; CHECK-VS1-NEXT: br i1 [[CMP_N10]], label %[[WHILE_END ]], label %[[VEC_EPILOG_SCALAR_PH]]
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+ ; CHECK-VS1-NEXT: br i1 [[CMP_N10]], label %[[WHILE_END_LOOPEXIT ]], label %[[VEC_EPILOG_SCALAR_PH]]
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; CHECK-VS1: [[VEC_EPILOG_SCALAR_PH]]:
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; CHECK-VS1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP39]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END4]], %[[VEC_EPILOG_ITER_CHECK]] ], [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ], [ [[TMP0]], %[[ITER_CHECK]] ]
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; CHECK-VS1-NEXT: br label %[[WHILE_BODY:.*]]
@@ -136,7 +136,9 @@ define void @low_vf_ic_is_better(ptr nocapture noundef %p, i32 %tc, i16 noundef
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; CHECK-VS1-NEXT: store i8 [[ADD]], ptr [[ARRAYIDX]], align 1
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; CHECK-VS1-NEXT: [[TMP38:%.*]] = and i64 [[IV_NEXT]], 4294967295
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; CHECK-VS1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[TMP38]], 19
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- ; CHECK-VS1-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END]], label %[[WHILE_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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+ ; CHECK-VS1-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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+ ; CHECK-VS1: [[WHILE_END_LOOPEXIT]]:
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+ ; CHECK-VS1-NEXT: br label %[[WHILE_END]]
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; CHECK-VS1: [[WHILE_END]]:
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; CHECK-VS1-NEXT: ret void
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;
@@ -194,7 +196,7 @@ define void @low_vf_ic_is_better(ptr nocapture noundef %p, i32 %tc, i16 noundef
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; CHECK-VS2-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK-VS2: [[MIDDLE_BLOCK]]:
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; CHECK-VS2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
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- ; CHECK-VS2-NEXT: br i1 [[CMP_N]], label %[[WHILE_END ]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
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+ ; CHECK-VS2-NEXT: br i1 [[CMP_N]], label %[[WHILE_END_LOOPEXIT:.* ]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
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; CHECK-VS2: [[VEC_EPILOG_ITER_CHECK]]:
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; CHECK-VS2-NEXT: [[IND_END4:%.*]] = add i64 [[TMP0]], [[N_VEC]]
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; CHECK-VS2-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[TMP3]], [[N_VEC]]
@@ -227,7 +229,7 @@ define void @low_vf_ic_is_better(ptr nocapture noundef %p, i32 %tc, i16 noundef
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; CHECK-VS2-NEXT: br i1 [[TMP36]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK-VS2: [[VEC_EPILOG_MIDDLE_BLOCK]]:
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; CHECK-VS2-NEXT: [[CMP_N10:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC3]]
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- ; CHECK-VS2-NEXT: br i1 [[CMP_N10]], label %[[WHILE_END ]], label %[[VEC_EPILOG_SCALAR_PH]]
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+ ; CHECK-VS2-NEXT: br i1 [[CMP_N10]], label %[[WHILE_END_LOOPEXIT ]], label %[[VEC_EPILOG_SCALAR_PH]]
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; CHECK-VS2: [[VEC_EPILOG_SCALAR_PH]]:
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; CHECK-VS2-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP39]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END4]], %[[VEC_EPILOG_ITER_CHECK]] ], [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ], [ [[TMP0]], %[[ITER_CHECK]] ]
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; CHECK-VS2-NEXT: br label %[[WHILE_BODY:.*]]
@@ -240,7 +242,9 @@ define void @low_vf_ic_is_better(ptr nocapture noundef %p, i32 %tc, i16 noundef
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; CHECK-VS2-NEXT: store i8 [[ADD]], ptr [[ARRAYIDX]], align 1
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; CHECK-VS2-NEXT: [[TMP38:%.*]] = and i64 [[IV_NEXT]], 4294967295
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; CHECK-VS2-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[TMP38]], 19
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- ; CHECK-VS2-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END]], label %[[WHILE_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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+ ; CHECK-VS2-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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+ ; CHECK-VS2: [[WHILE_END_LOOPEXIT]]:
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+ ; CHECK-VS2-NEXT: br label %[[WHILE_END]]
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; CHECK-VS2: [[WHILE_END]]:
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; CHECK-VS2-NEXT: ret void
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;
@@ -289,7 +293,9 @@ define void @trip_count_too_small(ptr nocapture noundef %p, i32 noundef %tc, i16
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; CHECK-NEXT: store i8 [[ADD]], ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[TMP44:%.*]] = and i64 [[INDVARS_IV_NEXT]], 4294967295
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[TMP44]], 3
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- ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END]], label %[[WHILE_BODY]]
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+ ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END_LOOPEXIT:.*]], label %[[WHILE_BODY]]
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+ ; CHECK: [[WHILE_END_LOOPEXIT]]:
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+ ; CHECK-NEXT: br label %[[WHILE_END]]
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; CHECK: [[WHILE_END]]:
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; CHECK-NEXT: ret void
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;
@@ -347,7 +353,9 @@ define void @too_many_runtime_checks(ptr nocapture noundef %p, ptr nocapture nou
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[TMP64:%.*]] = and i64 [[INDVARS_IV_NEXT]], 4294967295
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[TMP64]], 16
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- ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END]], label %[[WHILE_BODY]]
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+ ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END_LOOPEXIT:.*]], label %[[WHILE_BODY]]
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+ ; CHECK: [[WHILE_END_LOOPEXIT]]:
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+ ; CHECK-NEXT: br label %[[WHILE_END]]
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; CHECK: [[WHILE_END]]:
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; CHECK-NEXT: ret void
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;
@@ -398,6 +406,8 @@ define void @overflow_indvar_known_false(ptr nocapture noundef %p, i32 noundef %
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; CHECK-NEXT: [[TMP19:%.*]] = add i32 [[TC]], 1
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; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
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; CHECK-NEXT: [[TMP1:%.*]] = sub i64 1028, [[TMP20]]
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+ ; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
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+ ; CHECK: [[VECTOR_SCEVCHECK]]:
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; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TC]], 1
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; CHECK-NEXT: [[TMP22:%.*]] = zext i32 [[TMP21]] to i64
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; CHECK-NEXT: [[TMP23:%.*]] = sub i64 1027, [[TMP22]]
@@ -406,7 +416,7 @@ define void @overflow_indvar_known_false(ptr nocapture noundef %p, i32 noundef %
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; CHECK-NEXT: [[TMP26:%.*]] = icmp ult i32 [[TMP25]], [[TMP21]]
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; CHECK-NEXT: [[TMP27:%.*]] = icmp ugt i64 [[TMP23]], 4294967295
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; CHECK-NEXT: [[TMP28:%.*]] = or i1 [[TMP26]], [[TMP27]]
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- ; CHECK-NEXT: br i1 [[TMP28]], label %[[WHILE_BODY:.* ]], label %[[VECTOR_PH:.*]]
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+ ; CHECK-NEXT: br i1 [[TMP28]], label %[[SCALAR_PH ]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 16
@@ -434,17 +444,24 @@ define void @overflow_indvar_known_false(ptr nocapture noundef %p, i32 noundef %
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; CHECK-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX_NEXT]], i64 [[TMP1]])
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; CHECK-NEXT: [[TMP16:%.*]] = xor <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], splat (i1 true)
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; CHECK-NEXT: [[TMP17:%.*]] = extractelement <vscale x 16 x i1> [[TMP16]], i32 0
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- ; CHECK-NEXT: br i1 [[TMP17]], label %[[WHILE_END]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
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+ ; CHECK-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
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+ ; CHECK: [[MIDDLE_BLOCK]]:
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+ ; CHECK-NEXT: br i1 true, label %[[WHILE_END_LOOPEXIT:.*]], label %[[SCALAR_PH]]
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+ ; CHECK: [[SCALAR_PH]]:
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+ ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[TMP0]], %[[WHILE_PREHEADER]] ], [ [[TMP0]], %[[VECTOR_SCEVCHECK]] ]
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+ ; CHECK-NEXT: br label %[[WHILE_BODY:.*]]
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; CHECK: [[WHILE_BODY]]:
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- ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.* ]], %[[WHILE_BODY ]] ], [ [[TMP0 ]], %[[WHILE_PREHEADER ]] ]
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+ ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL ]], %[[SCALAR_PH ]] ], [ [[INDVARS_IV_NEXT:%.* ]], %[[WHILE_BODY ]] ]
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw i8, ptr [[V]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: [[TMP18:%.*]] = load i8, ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[ADD:%.*]] = add i8 [[TMP18]], [[CONV]]
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; CHECK-NEXT: store i8 [[ADD]], ptr [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[TMP29:%.*]] = and i64 [[INDVARS_IV_NEXT]], 4294967295
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[TMP29]], 1027
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- ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END]], label %[[WHILE_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
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+ ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[WHILE_END_LOOPEXIT]], label %[[WHILE_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
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+ ; CHECK: [[WHILE_END_LOOPEXIT]]:
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+ ; CHECK-NEXT: br label %[[WHILE_END]]
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; CHECK: [[WHILE_END]]:
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; CHECK-NEXT: ret void
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;
@@ -477,15 +494,38 @@ while.end:
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define i32 @tc4 (ptr noundef readonly captures(none) %tmp ) vscale_range(1 ,16 ) {
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; CHECK-LABEL: define i32 @tc4(
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; CHECK-SAME: ptr noundef readonly captures(none) [[TMP:%.*]]) #[[ATTR1]] {
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- ; CHECK-NEXT: [[ENTRY:.*:]]
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- ; CHECK-NEXT: [[INDVARS_IV:%.*]] = add i64 0, 0
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- ; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [4 x i32], ptr [[TMP]], i64 0, i64 [[INDVARS_IV]]
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+ ; CHECK-NEXT: [[ENTRY:.*]]:
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+ ; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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+ ; CHECK: [[VECTOR_PH]]:
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+ ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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+ ; CHECK: [[VECTOR_BODY]]:
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+ ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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+ ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
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+ ; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds nuw [4 x i32], ptr [[TMP]], i64 0, i64 [[INDEX]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw i32, ptr [[ARRAYIDX1]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4
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- ; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> zeroinitializer, [[WIDE_LOAD]]
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- ; CHECK-NEXT: [[INDEX_NEXT:%.*]] = add nuw i64 0, 4
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+ ; CHECK-NEXT: [[TMP3]] = add <4 x i32> [[VEC_PHI]], [[WIDE_LOAD]]
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+ ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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+ ; CHECK-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
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+ ; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP3]])
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- ; CHECK-NEXT: ret i32 [[TMP4]]
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+ ; CHECK-NEXT: br i1 true, label %[[FOR_COND_CLEANUP:.*]], label %[[SCALAR_PH]]
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+ ; CHECK: [[SCALAR_PH]]:
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+ ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 4, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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+ ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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+ ; CHECK-NEXT: br label %[[FOR_BODY:.*]]
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+ ; CHECK: [[FOR_COND_CLEANUP]]:
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+ ; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD:%.*]], %[[FOR_BODY]] ], [ [[TMP4]], %[[MIDDLE_BLOCK]] ]
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+ ; CHECK-NEXT: ret i32 [[ADD_LCSSA]]
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+ ; CHECK: [[FOR_BODY]]:
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+ ; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
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+ ; CHECK-NEXT: [[SUM_0179:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[ADD]], %[[FOR_BODY]] ]
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+ ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4 x i32], ptr [[TMP]], i64 0, i64 [[INDVARS_IV]]
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+ ; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
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+ ; CHECK-NEXT: [[ADD]] = add i32 [[SUM_0179]], [[TMP5]]
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+ ; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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+ ; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4
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+ ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
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;
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entry:
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br label %for.body
@@ -522,7 +562,7 @@ define i32 @tc4_from_profile(ptr noundef readonly captures(none) %tmp, i64 %N) v
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; CHECK-NEXT: [[ADD]] = add i32 [[SUM_0179]], [[TMP0]]
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]]
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- ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !prof [[PROF7 :![0-9]+]]
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+ ; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY]], !prof [[PROF9 :![0-9]+]]
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;
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entry:
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br label %for.body
@@ -555,7 +595,9 @@ for.body: ; preds = %entry, %for.body
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; CHECK-VS1: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]]}
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; CHECK-VS1: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}
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; CHECK-VS1: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]]}
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- ; CHECK-VS1: [[PROF7]] = !{!"branch_weights", i32 10, i32 30}
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+ ; CHECK-VS1: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}
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+ ; CHECK-VS1: [[LOOP8]] = distinct !{[[LOOP8]], [[META2]], [[META1]]}
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+ ; CHECK-VS1: [[PROF9]] = !{!"branch_weights", i32 10, i32 30}
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;.
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; CHECK-VS2: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK-VS2: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
@@ -564,5 +606,7 @@ for.body: ; preds = %entry, %for.body
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; CHECK-VS2: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]]}
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; CHECK-VS2: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}
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; CHECK-VS2: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]]}
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- ; CHECK-VS2: [[PROF7]] = !{!"branch_weights", i32 10, i32 30}
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+ ; CHECK-VS2: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}
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+ ; CHECK-VS2: [[LOOP8]] = distinct !{[[LOOP8]], [[META2]], [[META1]]}
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+ ; CHECK-VS2: [[PROF9]] = !{!"branch_weights", i32 10, i32 30}
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;.
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