Skip to content

Commit b072ec5

Browse files
SisyphSisyph
committed
[AMDGPU] NFC. Run auto-update on a few tests
1 parent 30e8dcd commit b072ec5

File tree

4 files changed

+12
-14
lines changed

4 files changed

+12
-14
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m
1414
; GCN-NEXT: v_mov_b32_e32 v4, s1
1515
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1616
; GCN-NEXT: v_interp_p10_f32 v3, v0, v2, v0 wait_exp:1
17-
; GCN-NEXT: v_interp_p10_f32 v2, v1, v2, v1
17+
; GCN-NEXT: v_interp_p10_f32 v2, v1, v2, v1 wait_exp:0
1818
; GCN-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7
1919
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
2020
; GCN-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7
@@ -47,7 +47,7 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr
4747
; GCN-NEXT: v_interp_p10_f32 v6, v0, v4, v0 wait_exp:3
4848
; GCN-NEXT: v_interp_p10_f32 v7, v1, v4, v1 wait_exp:2
4949
; GCN-NEXT: v_interp_p10_f32 v8, v2, v4, v2 wait_exp:1
50-
; GCN-NEXT: v_interp_p10_f32 v4, v3, v4, v3
50+
; GCN-NEXT: v_interp_p10_f32 v4, v3, v4, v3 wait_exp:0
5151
; GCN-NEXT: v_interp_p2_f32 v6, v0, v5, v6 wait_exp:7
5252
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
5353
; GCN-NEXT: v_interp_p2_f32 v7, v1, v5, v7 wait_exp:7
@@ -89,7 +89,7 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0
8989
; GCN-NEXT: v_interp_p10_f32 v6, v2, v0, v2 wait_exp:3
9090
; GCN-NEXT: v_interp_p10_f32 v7, v3, v0, v3 wait_exp:2
9191
; GCN-NEXT: v_interp_p10_f32 v8, v4, v0, v4 wait_exp:1
92-
; GCN-NEXT: v_interp_p10_f32 v0, v5, v0, v5
92+
; GCN-NEXT: v_interp_p10_f32 v0, v5, v0, v5 wait_exp:0
9393
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
9494
; GCN-NEXT: v_interp_p2_f32 v6, v2, v1, v6 wait_exp:7
9595
; GCN-NEXT: v_interp_p2_f32 v7, v3, v1, v7 wait_exp:7
@@ -130,7 +130,7 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
130130
; GCN-NEXT: v_mov_b32_e32 v0, s0
131131
; GCN-NEXT: v_mov_b32_e32 v2, s1
132132
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
133-
; GCN-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1
133+
; GCN-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0
134134
; GCN-NEXT: v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
135135
; GCN-NEXT: v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7
136136
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)

‎llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define amdgpu_ps void @_amdgpu_ps_main(i32 inreg %PrimMask, <2 x float> %InterpC
1818
; GCN-NEXT: v_mbcnt_hi_u32_b32 v8, -1, v8
1919
; GCN-NEXT: v_interp_p10_f32 v9, v5, v3, v5 wait_exp:2
2020
; GCN-NEXT: v_interp_p10_f32 v11, v6, v3, v6 wait_exp:1
21-
; GCN-NEXT: v_interp_p10_f32 v10, v7, v3, v7
21+
; GCN-NEXT: v_interp_p10_f32 v10, v7, v3, v7 wait_exp:0
2222
; GCN-NEXT: v_interp_p10_f32 v3, v4, v3, v4 wait_exp:7
2323
; GCN-NEXT: v_interp_p2_f32 v5, v5, v2, v9 wait_exp:7
2424
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m
1414
; GCN-NEXT: v_mov_b32_e32 v4, s1
1515
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
1616
; GCN-NEXT: v_interp_p10_f32 v3, v0, v2, v0 wait_exp:1
17-
; GCN-NEXT: v_interp_p10_f32 v2, v1, v2, v1
17+
; GCN-NEXT: v_interp_p10_f32 v2, v1, v2, v1 wait_exp:0
1818
; GCN-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7
1919
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
2020
; GCN-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7
@@ -47,7 +47,7 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr
4747
; GCN-NEXT: v_interp_p10_f32 v6, v0, v4, v0 wait_exp:3
4848
; GCN-NEXT: v_interp_p10_f32 v7, v1, v4, v1 wait_exp:2
4949
; GCN-NEXT: v_interp_p10_f32 v8, v2, v4, v2 wait_exp:1
50-
; GCN-NEXT: v_interp_p10_f32 v4, v3, v4, v3
50+
; GCN-NEXT: v_interp_p10_f32 v4, v3, v4, v3 wait_exp:0
5151
; GCN-NEXT: v_interp_p2_f32 v6, v0, v5, v6 wait_exp:7
5252
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
5353
; GCN-NEXT: v_interp_p2_f32 v7, v1, v5, v7 wait_exp:7
@@ -89,7 +89,7 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0
8989
; GCN-NEXT: v_interp_p10_f32 v6, v2, v0, v2 wait_exp:3
9090
; GCN-NEXT: v_interp_p10_f32 v7, v3, v0, v3 wait_exp:2
9191
; GCN-NEXT: v_interp_p10_f32 v8, v4, v0, v4 wait_exp:1
92-
; GCN-NEXT: v_interp_p10_f32 v0, v5, v0, v5
92+
; GCN-NEXT: v_interp_p10_f32 v0, v5, v0, v5 wait_exp:0
9393
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
9494
; GCN-NEXT: v_interp_p2_f32 v6, v2, v1, v6 wait_exp:7
9595
; GCN-NEXT: v_interp_p2_f32 v7, v3, v1, v7 wait_exp:7
@@ -130,7 +130,7 @@ define amdgpu_ps half @v_interp_f16(float inreg %i, float inreg %j, i32 inreg %m
130130
; GCN-NEXT: v_mov_b32_e32 v0, s0
131131
; GCN-NEXT: v_mov_b32_e32 v2, s1
132132
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
133-
; GCN-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1
133+
; GCN-NEXT: v_interp_p10_f16_f32 v3, v1, v0, v1 wait_exp:0
134134
; GCN-NEXT: v_interp_p10_f16_f32 v0, v1, v0, v1 op_sel:[1,0,1,0] wait_exp:7
135135
; GCN-NEXT: v_interp_p2_f16_f32 v3, v1, v2, v3 wait_exp:7
136136
; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)

‎llvm/test/CodeGen/AMDGPU/ptr-arg-dbg-value.ll

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@
99
define hidden void @ptr_arg_split_subregs(ptr %arg1) #0 !dbg !9 {
1010
; CHECK-LABEL: ptr_arg_split_subregs:
1111
; CHECK: .Lfunc_begin0:
12-
; CHECK: .loc 1 5 0 ; example.cpp:5:0
12+
; CHECK-NEXT: .file 1 "temp" "example.cpp"
13+
; CHECK-NEXT: .loc 1 5 0 ; example.cpp:5:0
1314
; CHECK-NEXT: .cfi_sections .debug_frame
1415
; CHECK-NEXT: .cfi_startproc
1516
; CHECK-NEXT: ; %bb.0:
@@ -24,7 +25,6 @@ define hidden void @ptr_arg_split_subregs(ptr %arg1) #0 !dbg !9 {
2425
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
2526
; CHECK-NEXT: s_setpc_b64 s[30:31]
2627
; CHECK-NEXT: .Ltmp1:
27-
; CHECK: .cfi_endproc
2828
call void @llvm.dbg.declare(metadata ptr %arg1, metadata !20, metadata !DIExpression()), !dbg !21
2929
%gep1 = getelementptr inbounds %struct.A, ptr %arg1, i32 0, i32 0, i32 99, !dbg !22
3030
store i32 1, ptr %gep1, align 4, !dbg !23
@@ -45,7 +45,7 @@ define hidden void @ptr_arg_split_reg_mem(<30 x i32>, ptr %arg2) #0 !dbg !25 {
4545
; CHECK-NEXT: ; %bb.0:
4646
; CHECK-NEXT: ;DEBUG_VALUE: ptr_arg_split_reg_mem:b <- [$vgpr30+0]
4747
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
48-
; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32{{$}}
48+
; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32
4949
; CHECK-NEXT: v_mov_b32_e32 v0, 1
5050
; CHECK-NEXT: .Ltmp2:
5151
; CHECK-NEXT: .loc 1 12 13 prologue_end ; example.cpp:12:13
@@ -55,7 +55,6 @@ define hidden void @ptr_arg_split_reg_mem(<30 x i32>, ptr %arg2) #0 !dbg !25 {
5555
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
5656
; CHECK-NEXT: s_setpc_b64 s[30:31]
5757
; CHECK-NEXT: .Ltmp3:
58-
; CHECK: .cfi_endproc
5958
call void @llvm.dbg.declare(metadata ptr %arg2, metadata !26, metadata !DIExpression()), !dbg !27
6059
%gep2 = getelementptr inbounds %struct.A, ptr %arg2, i32 0, i32 0, i32 99, !dbg !28
6160
store i32 1, ptr %gep2, align 4, !dbg !29
@@ -82,7 +81,6 @@ define hidden void @ptr_arg_in_memory(<32 x i32>, ptr %arg3) #0 !dbg !31 {
8281
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
8382
; CHECK-NEXT: s_setpc_b64 s[30:31]
8483
; CHECK-NEXT: .Ltmp5:
85-
; CHECK: .cfi_endproc
8684
call void @llvm.dbg.declare(metadata ptr %arg3, metadata !32, metadata !DIExpression()), !dbg !33
8785
%gep3 = getelementptr inbounds %struct.A, ptr %arg3, i32 0, i32 0, i32 99, !dbg !34
8886
store i32 1, ptr %gep3, align 4, !dbg !35

0 commit comments

Comments
 (0)