AMDGPU/MC: Refactor decoders. Rework decoders for float immediates

decodeFPImmed creates immediate operand using register operand width,
but size of created immediate should correspond to OperandType for
RegisterOperand.
e.g. OPW128 could be used for RegisterOperands that use v2f64 v4f32
and v8f16. Each RegisterOperands would have different OperandType and
require that immediate is decoded using 64, 32 and 16 bit immediate
respectively.
decodeOperand_<RegClass> only provides width for register decoding,
introduce decodeOperand_<RegClass>_Imm<ImmWidth> that also provides
width for immediate decoding.
Refactor RegisterOperands:
 - decoders get _Imm<ImmWidth> suffix in some cases
 - removed unused RegisterOperands defined via multiclass
 - use different RegisterOperand in a few places, new RegisterOperand's
   decoder corresponds to the number of bits used for operand's encoding
Refactor decoder functions:
 - add asserts for the size of encoding that will be decoded
 - regroup them according to the method of decoding
decodeOperand_<RegClass> (register only, no immediate) decoders can now
create immediate of consistent size, use it for better diagnostic of
'invalid immediate'.

Differential Revision: https://reviews.llvm.org/D142636

Author: petar-avramovic

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

@@ -166,58 +166,6 @@ class AMDGPUDisassembler : public MCDisassembler {
   DecodeStatus convertVOPCDPPInst(MCInst &MI) const;
   void convertMacDPPInst(MCInst &MI) const;
 
-  MCOperand decodeOperand_VGPR_32(unsigned Val) const;
-  MCOperand decodeOperand_VGPR_32_Lo128(unsigned Val) const;
-  MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
-
-  MCOperand decodeOperand_VS_32(unsigned Val) const;
-  MCOperand decodeOperand_VS_64(unsigned Val) const;
-  MCOperand decodeOperand_VS_128(unsigned Val) const;
-  MCOperand decodeOperand_VSrc16(unsigned Val) const;
-  MCOperand decodeOperand_VSrcV216(unsigned Val) const;
-  MCOperand decodeOperand_VSrcV232(unsigned Val) const;
-
-  MCOperand decodeOperand_VReg_64(unsigned Val) const;
-  MCOperand decodeOperand_VReg_96(unsigned Val) const;
-  MCOperand decodeOperand_VReg_128(unsigned Val) const;
-  MCOperand decodeOperand_VReg_256(unsigned Val) const;
-  MCOperand decodeOperand_VReg_288(unsigned Val) const;
-  MCOperand decodeOperand_VReg_320(unsigned Val) const;
-  MCOperand decodeOperand_VReg_352(unsigned Val) const;
-  MCOperand decodeOperand_VReg_384(unsigned Val) const;
-  MCOperand decodeOperand_VReg_512(unsigned Val) const;
-  MCOperand decodeOperand_VReg_1024(unsigned Val) const;
-
-  MCOperand decodeOperand_SReg_32(unsigned Val) const;
-  MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const;
-  MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const;
-  MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const;
-  MCOperand decodeOperand_SReg_64(unsigned Val) const;
-  MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const;
-  MCOperand decodeOperand_SReg_128(unsigned Val) const;
-  MCOperand decodeOperand_SReg_256(unsigned Val) const;
-  MCOperand decodeOperand_SReg_288(unsigned Val) const;
-  MCOperand decodeOperand_SReg_320(unsigned Val) const;
-  MCOperand decodeOperand_SReg_352(unsigned Val) const;
-  MCOperand decodeOperand_SReg_384(unsigned Val) const;
-  MCOperand decodeOperand_SReg_512(unsigned Val) const;
-
-  MCOperand decodeOperand_AGPR_32(unsigned Val) const;
-  MCOperand decodeOperand_AReg_64(unsigned Val) const;
-  MCOperand decodeOperand_AReg_128(unsigned Val) const;
-  MCOperand decodeOperand_AReg_256(unsigned Val) const;
-  MCOperand decodeOperand_AReg_288(unsigned Val) const;
-  MCOperand decodeOperand_AReg_320(unsigned Val) const;
-  MCOperand decodeOperand_AReg_352(unsigned Val) const;
-  MCOperand decodeOperand_AReg_384(unsigned Val) const;
-  MCOperand decodeOperand_AReg_512(unsigned Val) const;
-  MCOperand decodeOperand_AReg_1024(unsigned Val) const;
-  MCOperand decodeOperand_AV_32(unsigned Val) const;
-  MCOperand decodeOperand_AV_64(unsigned Val) const;
-  MCOperand decodeOperand_AV_128(unsigned Val) const;
-  MCOperand decodeOperand_AVDst_128(unsigned Val) const;
-  MCOperand decodeOperand_AVDst_512(unsigned Val) const;
-
   enum OpWidthTy {
     OPW32,
     OPW64,
@@ -244,18 +192,21 @@ class AMDGPUDisassembler : public MCDisassembler {
   unsigned getTtmpClassId(const OpWidthTy Width) const;
 
   static MCOperand decodeIntImmed(unsigned Imm);
-  static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm);
+  static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm);
+
   MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
   MCOperand decodeLiteralConstant() const;
 
   MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val,
-                        bool MandatoryLiteral = false) const;
-  MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const;
+                        bool MandatoryLiteral = false,
+                        unsigned ImmWidth = 0) const;
+
   MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
   MCOperand decodeSpecialReg32(unsigned Val) const;
   MCOperand decodeSpecialReg64(unsigned Val) const;
 
-  MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const;
+  MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val,
+                          unsigned ImmWidth = 0) const;
   MCOperand decodeSDWASrc16(unsigned Val) const;
   MCOperand decodeSDWASrc32(unsigned Val) const;
   MCOperand decodeSDWAVopcDst(unsigned Val) const;

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

@@ -737,9 +737,10 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
       O << formatDec(Op.getImm());
       break;
     case MCOI::OPERAND_REGISTER:
-      // FIXME: This should be removed and handled somewhere else. Seems to come
-      // from a disassembler bug.
-      O << "/*invalid immediate*/";
+      // Disassembler does not fail when operand should not allow immediate
+      // operands but decodes them into 32bit immediate operand.
+      printImmediate32(Op.getImm(), STI, O);
+      O << "/*Invalid immediate*/";
       break;
     default:
       // We hit this for the immediate instruction bits that don't yet have a

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

@@ -1707,7 +1707,7 @@ class getVOP3SrcForVT<ValueType VT> {
   bit isFP = isFloatType<VT>.ret;
   RegisterOperand ret =
   !if(!eq(VT.Size, 128),
-     VSrc_128,
+     VRegSrc_128,
      !if(!eq(VT.Size, 64),
         !if(isFP,
            !if(!eq(VT.Value, v2f32.Value),
@@ -2435,7 +2435,7 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableClamp = 0> {
   field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret;
   field RegisterClass Src2DPP = getVregSrcForVT<Src2VT>.ret;
   field RegisterOperand Src0VOP3DPP = VGPRSrc_32;
-  field RegisterOperand Src1VOP3DPP = VGPRSrc_32;
+  field RegisterOperand Src1VOP3DPP = VRegSrc_32;
   field RegisterOperand Src2VOP3DPP = getVOP3DPPSrcForVT<Src2VT>.ret;
   field RegisterOperand Src0SDWA = getSDWASrcForVT<Src0VT>.ret;
   field RegisterOperand Src1SDWA = getSDWASrcForVT<Src0VT>.ret;