Skip to content

Commit b185e92

Browse files
momchil-velikovLukacma
momchil-velikov
and
Lukacma
authored
[AArch64] Add assembly/disassembly for {S,U,SU,US}TMOPA instructions (#113946)
The new instructions are described in https://developer.arm.com/documentation/ddi0602/2024-09/SME-Instructions Co-Authored-By: Marian Lukac <[email protected]>
1 parent 18f0f70 commit b185e92

File tree

10 files changed

+550
-0
lines changed

10 files changed

+550
-0
lines changed

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -158,6 +158,15 @@ let Predicates = [HasSME2p2, HasSMEI16I64] in {
158158
defm USMOP4S : sme_quarter_outer_product_i64<0b1, 0b0, 0b1, "usmop4s">;
159159
}
160160

161+
let Predicates = [HasSME2p2] in {
162+
def STMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b00100, ZZ_b_mul_r, ZPR8, "stmopa">;
163+
def STMOPA_M2ZZZI_HtoS : sme_int_sparse_outer_product_i32<0b00101, ZZ_h_mul_r, ZPR16, "stmopa">;
164+
def UTMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b11100, ZZ_b_mul_r, ZPR8, "utmopa">;
165+
def UTMOPA_M2ZZZI_HtoS : sme_int_sparse_outer_product_i32<0b10101, ZZ_h_mul_r, ZPR16, "utmopa">;
166+
def SUTMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b01100, ZZ_b_mul_r, ZPR8, "sutmopa">;
167+
def USTMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b10100, ZZ_b_mul_r, ZPR8, "ustmopa">;
168+
}
169+
161170
let Predicates = [HasSME] in {
162171
//===----------------------------------------------------------------------===//
163172
// Loads and stores

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -390,6 +390,35 @@ multiclass sme_int_outer_product_i64<bits<3> opc, string mnemonic,
390390
def : SME_ZA_Tile_TwoPred_TwoVec_Pat<NAME, op, timm32_0_7, nxv8i1, nxv8i16>;
391391
}
392392

393+
class sme_int_sparse_outer_product_i32<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
394+
: I<(outs TileOp32:$ZAda),
395+
(ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm, ZK:$Zk, VectorIndexS32b:$imm),
396+
mnemonic, "\t$ZAda, $Zn, $Zm, $Zk$imm",
397+
"", []>,
398+
Sched<[]> {
399+
bits<2> ZAda;
400+
bits<4> Zn;
401+
bits<5> Zm;
402+
bits<3> Zk;
403+
bits<2> imm;
404+
let Inst{31-25} = 0b1000000;
405+
let Inst{24} = opc{4};
406+
let Inst{23-22} = 0b01;
407+
let Inst{21} = opc{3};
408+
let Inst{20-16} = Zm;
409+
let Inst{15} = opc{2};
410+
let Inst{14} = 0b0;
411+
let Inst{13} = opc{1};
412+
let Inst{12-10} = Zk;
413+
let Inst{9-6} = Zn;
414+
let Inst{5-4} = imm;
415+
let Inst{3} = opc{0};
416+
let Inst{2} = 0b0;
417+
let Inst{1-0} = ZAda;
418+
419+
let Constraints = "$ZAda = $_ZAda";
420+
}
421+
393422
class sme_outer_product_widening_inst<bits<3> opc, ZPRRegOp zpr_ty, string mnemonic>
394423
: I<(outs TileOp32:$ZAda),
395424
(ins TileOp32:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),

‎llvm/test/MC/AArch64/SME2p2/stmopa-diagnostics.s

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid ZA register
5+
6+
stmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: stmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
stmopa za4.s, {z30.h-z31.h}, z31.h, z31[3]
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
13+
// CHECK-NEXT: stmopa za4.s, {z30.h-z31.h}, z31.h, z31[3]
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
// --------------------------------------------------------------------------//
17+
// Invalid vector list operand
18+
19+
stmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
20+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
21+
// CHECK-NEXT: stmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
22+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
23+
24+
stmopa za3.s, {z29.h-z30.h}, z31.h, z31[3]
25+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
26+
// CHECK-NEXT: stmopa za3.s, {z29.h-z30.h}, z31.h, z31[3]
27+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28+
29+
// --------------------------------------------------------------------------//
30+
// Invalid ZK register
31+
stmopa za3.s, {z28.b-z29.b}, z31.b, z19[3]
32+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
33+
// CHECK-NEXT: stmopa za3.s, {z28.b-z29.b}, z31.b, z19[3]
34+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35+
36+
stmopa za3.s, {z28.b-z29.b}, z31.b, z24[3]
37+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
38+
// CHECK-NEXT: stmopa za3.s, {z28.b-z29.b}, z31.b, z24[3]
39+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
40+
41+
stmopa za3.s, {z28.b-z29.b}, z31.b, z27[3]
42+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
43+
// CHECK-NEXT: stmopa za3.s, {z28.b-z29.b}, z31.b, z27[3]
44+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
45+
46+
stmopa za3.s, {z28.h-z29.h}, z31.h, z19[3]
47+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
48+
// CHECK-NEXT: stmopa za3.s, {z28.h-z29.h}, z31.h, z19[3]
49+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
50+
51+
stmopa za3.s, {z28.h-z29.h}, z31.h, z24[3]
52+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
53+
// CHECK-NEXT: stmopa za3.s, {z28.h-z29.h}, z31.h, z24[3]
54+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
55+
56+
stmopa za3.s, {z28.h-z29.h}, z31.h, z27[3]
57+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
58+
// CHECK-NEXT: stmopa za3.s, {z28.h-z29.h}, z31.h, z27[3]
59+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
60+
61+
// --------------------------------------------------------------------------//
62+
// Invalid immediate
63+
64+
stmopa za3.s, {z28.b-z29.b}, z31.b, z20[4]
65+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
66+
// CHECK-NEXT: stmopa za3.s, {z28.b-z29.b}, z31.b, z20[4]
67+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
68+
69+
stmopa za3.s, {z28.h-z29.h}, z31.h, z20[4]
70+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
71+
// CHECK-NEXT: stmopa za3.s, {z28.h-z29.h}, z31.h, z20[4]
72+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
73+
74+
// --------------------------------------------------------------------------//
75+
// Invalid ZPR type suffix
76+
77+
stmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
78+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
79+
// CHECK-NEXT: stmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
80+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
81+
82+
stmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
83+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
84+
// CHECK-NEXT: stmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
85+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
86+
87+
stmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
88+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
89+
// CHECK-NEXT: stmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
90+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
91+
92+
stmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
93+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
94+
// CHECK-NEXT: stmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
95+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
96+
97+
stmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
98+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
99+
// CHECK-NEXT: stmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
100+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SME2p2/stmopa.s

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
6+
// RUN: | llvm-objdump -d --mattr=+sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=-sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
10+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
11+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
12+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \
13+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
14+
15+
stmopa za0.s, {z0.b-z1.b}, z0.b, z20[0] // 10000000-01000000-10000000-00000000
16+
// CHECK-INST: stmopa za0.s, { z0.b, z1.b }, z0.b, z20[0]
17+
// CHECK-ENCODING: [0x00,0x80,0x40,0x80]
18+
// CHECK-ERROR: instruction requires: sme2p2
19+
// CHECK-UNKNOWN: 80408000 <unknown>
20+
21+
stmopa za3.s, {z12.b-z13.b}, z8.b, z23[3] // 10000000-01001000-10001101-10110011
22+
// CHECK-INST: stmopa za3.s, { z12.b, z13.b }, z8.b, z23[3]
23+
// CHECK-ENCODING: [0xb3,0x8d,0x48,0x80]
24+
// CHECK-ERROR: instruction requires: sme2p2
25+
// CHECK-UNKNOWN: 80488db3 <unknown>
26+
27+
stmopa za3.s, {z30.b-z31.b}, z31.b, z31[3] // 10000000-01011111-10011111-11110011
28+
// CHECK-INST: stmopa za3.s, { z30.b, z31.b }, z31.b, z31[3]
29+
// CHECK-ENCODING: [0xf3,0x9f,0x5f,0x80]
30+
// CHECK-ERROR: instruction requires: sme2p2
31+
// CHECK-UNKNOWN: 805f9ff3 <unknown>
32+
33+
stmopa za0.s, {z0.h-z1.h}, z0.h, z20[0] // 10000000-01000000-10000000-00001000
34+
// CHECK-INST: stmopa za0.s, { z0.h, z1.h }, z0.h, z20[0]
35+
// CHECK-ENCODING: [0x08,0x80,0x40,0x80]
36+
// CHECK-ERROR: instruction requires: sme2p2
37+
// CHECK-UNKNOWN: 80408008 <unknown>
38+
39+
stmopa za3.s, {z12.h-z13.h}, z8.h, z23[3] // 10000000-01001000-10001101-10111011
40+
// CHECK-INST: stmopa za3.s, { z12.h, z13.h }, z8.h, z23[3]
41+
// CHECK-ENCODING: [0xbb,0x8d,0x48,0x80]
42+
// CHECK-ERROR: instruction requires: sme2p2
43+
// CHECK-UNKNOWN: 80488dbb <unknown>
44+
45+
stmopa za3.s, {z30.h-z31.h}, z31.h, z31[3] // 10000000-01011111-10011111-11111011
46+
// CHECK-INST: stmopa za3.s, { z30.h, z31.h }, z31.h, z31[3]
47+
// CHECK-ENCODING: [0xfb,0x9f,0x5f,0x80]
48+
// CHECK-ERROR: instruction requires: sme2p2
49+
// CHECK-UNKNOWN: 805f9ffb <unknown>

‎llvm/test/MC/AArch64/SME2p2/sutmopa-diagnostics.s

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid ZA register
5+
6+
sutmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: sutmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
// --------------------------------------------------------------------------//
12+
// Invalid vector list operand
13+
14+
sutmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
15+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
16+
// CHECK-NEXT: sutmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
17+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18+
19+
// --------------------------------------------------------------------------//
20+
// Invalid ZK register
21+
22+
sutmopa za3.s, {z28.b-z29.b}, z31.b, z19[2]
23+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
24+
// CHECK-NEXT: sutmopa za3.s, {z28.b-z29.b}, z31.b, z19[2]
25+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26+
27+
sutmopa za3.s, {z28.b-z29.b}, z31.b, z24[2]
28+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
29+
// CHECK-NEXT: sutmopa za3.s, {z28.b-z29.b}, z31.b, z24[2]
30+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
31+
32+
sutmopa za3.s, {z28.b-z29.b}, z31.b, z27[2]
33+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
34+
// CHECK-NEXT: sutmopa za3.s, {z28.b-z29.b}, z31.b, z27[2]
35+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
36+
37+
// --------------------------------------------------------------------------//
38+
// Invalid immediate
39+
40+
sutmopa za3.s, {z28.b-z29.b}, z31.b, z29[4]
41+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
42+
// CHECK-NEXT: sutmopa za3.s, {z28.b-z29.b}, z31.b, z29[4]
43+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44+
45+
// --------------------------------------------------------------------------//
46+
// Invalid ZPR type suffix
47+
48+
sutmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
49+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
50+
// CHECK-NEXT: sutmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
51+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
52+
53+
sutmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
54+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
55+
// CHECK-NEXT: sutmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
56+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
57+
58+
sutmopa za3.s, {z28.h-z29.h}, z31.h, z20[3]
59+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
60+
// CHECK-NEXT: sutmopa za3.s, {z28.h-z29.h}, z31.h, z20[3]
61+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
62+
63+
sutmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
64+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
65+
// CHECK-NEXT: sutmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
66+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
67+
68+
sutmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
69+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
70+
// CHECK-NEXT: sutmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
71+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
72+
73+
sutmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
74+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
75+
// CHECK-NEXT: sutmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
76+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SME2p2/sutmopa.s

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,31 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
6+
// RUN: | llvm-objdump -d --mattr=+sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=-sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
10+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
11+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
12+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \
13+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
14+
15+
sutmopa za0.s, {z0.b-z1.b}, z0.b, z20[0] // 10000000-01100000-10000000-00000000
16+
// CHECK-INST: sutmopa za0.s, { z0.b, z1.b }, z0.b, z20[0]
17+
// CHECK-ENCODING: [0x00,0x80,0x60,0x80]
18+
// CHECK-ERROR: instruction requires: sme2p2
19+
// CHECK-UNKNOWN: 80608000 <unknown>
20+
21+
sutmopa za1.s, {z10.b-z11.b}, z21.b, z29[1] // 10000000-01110101-10010101-01010001
22+
// CHECK-INST: sutmopa za1.s, { z10.b, z11.b }, z21.b, z29[1]
23+
// CHECK-ENCODING: [0x51,0x95,0x75,0x80]
24+
// CHECK-ERROR: instruction requires: sme2p2
25+
// CHECK-UNKNOWN: 80759551 <unknown>
26+
27+
sutmopa za3.s, {z30.b-z31.b}, z31.b, z31[3] // 10000000-01111111-10011111-11110011
28+
// CHECK-INST: sutmopa za3.s, { z30.b, z31.b }, z31.b, z31[3]
29+
// CHECK-ENCODING: [0xf3,0x9f,0x7f,0x80]
30+
// CHECK-ERROR: instruction requires: sme2p2
31+
// CHECK-UNKNOWN: 807f9ff3 <unknown>

‎llvm/test/MC/AArch64/SME2p2/ustmopa-diagnostics.s

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,76 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid ZA register
5+
6+
ustmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: ustmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
// --------------------------------------------------------------------------//
12+
// Invalid vector list operand
13+
14+
ustmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
15+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
16+
// CHECK-NEXT: ustmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
17+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
18+
19+
// --------------------------------------------------------------------------//
20+
// Invalid ZK register
21+
22+
ustmopa za3.s, {z28.b-z29.b}, z31.b, z19[2]
23+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
24+
// CHECK-NEXT: ustmopa za3.s, {z28.b-z29.b}, z31.b, z19[2]
25+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
26+
27+
ustmopa za3.s, {z28.b-z29.b}, z31.b, z24[2]
28+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
29+
// CHECK-NEXT: ustmopa za3.s, {z28.b-z29.b}, z31.b, z24[2]
30+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
31+
32+
ustmopa za3.s, {z28.b-z29.b}, z31.b, z27[2]
33+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
34+
// CHECK-NEXT: ustmopa za3.s, {z28.b-z29.b}, z31.b, z27[2]
35+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
36+
37+
// --------------------------------------------------------------------------//
38+
// Invalid immediate
39+
40+
ustmopa za3.s, {z28.b-z29.b}, z31.b, z29[4]
41+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
42+
// CHECK-NEXT: ustmopa za3.s, {z28.b-z29.b}, z31.b, z29[4]
43+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
44+
45+
// --------------------------------------------------------------------------//
46+
// Invalid ZPR type suffix
47+
48+
ustmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
49+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
50+
// CHECK-NEXT: ustmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
51+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
52+
53+
ustmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
54+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
55+
// CHECK-NEXT: ustmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
56+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
57+
58+
ustmopa za3.s, {z28.h-z29.h}, z31.h, z20[3]
59+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
60+
// CHECK-NEXT: ustmopa za3.s, {z28.h-z29.h}, z31.h, z20[3]
61+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
62+
63+
ustmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
64+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
65+
// CHECK-NEXT: ustmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
66+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
67+
68+
ustmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
69+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
70+
// CHECK-NEXT: ustmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
71+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
72+
73+
ustmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
74+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
75+
// CHECK-NEXT: ustmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
76+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

0 commit comments

Comments
 (0)