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[InstCombine] Fold Ext(i1) Pred shr(A, BW - 1) => i1 Pred A s< 0 (#68244)
Resolves #67916 . This patch folds `Ext(icmp (A, xxx)) Pred shr(A, BW - 1)` into `i1 Pred A s< 0`. [Alive2](https://alive2.llvm.org/ce/z/k53Xwa).
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3 files changed

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lines changed

3 files changed

+249
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‎llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp

Lines changed: 27 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -5390,35 +5390,6 @@ Instruction *InstCombinerImpl::foldICmpEquality(ICmpInst &I) {
53905390
return new ICmpInst(Pred, A, Builder.CreateTrunc(B, A->getType()));
53915391
}
53925392

5393-
// Test if 2 values have different or same signbits:
5394-
// (X u>> BitWidth - 1) == zext (Y s> -1) --> (X ^ Y) < 0
5395-
// (X u>> BitWidth - 1) != zext (Y s> -1) --> (X ^ Y) > -1
5396-
// (X s>> BitWidth - 1) == sext (Y s> -1) --> (X ^ Y) < 0
5397-
// (X s>> BitWidth - 1) != sext (Y s> -1) --> (X ^ Y) > -1
5398-
Instruction *ExtI;
5399-
if (match(Op1, m_CombineAnd(m_Instruction(ExtI), m_ZExtOrSExt(m_Value(A)))) &&
5400-
(Op0->hasOneUse() || Op1->hasOneUse())) {
5401-
unsigned OpWidth = Op0->getType()->getScalarSizeInBits();
5402-
Instruction *ShiftI;
5403-
Value *X, *Y;
5404-
ICmpInst::Predicate Pred2;
5405-
if (match(Op0, m_CombineAnd(m_Instruction(ShiftI),
5406-
m_Shr(m_Value(X),
5407-
m_SpecificIntAllowUndef(OpWidth - 1)))) &&
5408-
match(A, m_ICmp(Pred2, m_Value(Y), m_AllOnes())) &&
5409-
Pred2 == ICmpInst::ICMP_SGT && X->getType() == Y->getType()) {
5410-
unsigned ExtOpc = ExtI->getOpcode();
5411-
unsigned ShiftOpc = ShiftI->getOpcode();
5412-
if ((ExtOpc == Instruction::ZExt && ShiftOpc == Instruction::LShr) ||
5413-
(ExtOpc == Instruction::SExt && ShiftOpc == Instruction::AShr)) {
5414-
Value *Xor = Builder.CreateXor(X, Y, "xor.signbits");
5415-
Value *R = (Pred == ICmpInst::ICMP_EQ) ? Builder.CreateIsNeg(Xor)
5416-
: Builder.CreateIsNotNeg(Xor);
5417-
return replaceInstUsesWith(I, R);
5418-
}
5419-
}
5420-
}
5421-
54225393
// (A >> C) == (B >> C) --> (A^B) u< (1 << C)
54235394
// For lshr and ashr pairs.
54245395
const APInt *AP1, *AP2;
@@ -7194,6 +7165,33 @@ Instruction *InstCombinerImpl::visitICmpInst(ICmpInst &I) {
71947165
if (Instruction *R = processUMulZExtIdiom(I, Op1, Op0, *this))
71957166
return R;
71967167
}
7168+
7169+
Value *X, *Y;
7170+
// Signbit test folds
7171+
// Fold (X u>> BitWidth - 1 Pred ZExt(i1)) --> X s< 0 Pred i1
7172+
// Fold (X s>> BitWidth - 1 Pred SExt(i1)) --> X s< 0 Pred i1
7173+
Instruction *ExtI;
7174+
if ((I.isUnsigned() || I.isEquality()) &&
7175+
match(Op1,
7176+
m_CombineAnd(m_Instruction(ExtI), m_ZExtOrSExt(m_Value(Y)))) &&
7177+
Y->getType()->getScalarSizeInBits() == 1 &&
7178+
(Op0->hasOneUse() || Op1->hasOneUse())) {
7179+
unsigned OpWidth = Op0->getType()->getScalarSizeInBits();
7180+
Instruction *ShiftI;
7181+
if (match(Op0, m_CombineAnd(m_Instruction(ShiftI),
7182+
m_Shr(m_Value(X), m_SpecificIntAllowUndef(
7183+
OpWidth - 1))))) {
7184+
unsigned ExtOpc = ExtI->getOpcode();
7185+
unsigned ShiftOpc = ShiftI->getOpcode();
7186+
if ((ExtOpc == Instruction::ZExt && ShiftOpc == Instruction::LShr) ||
7187+
(ExtOpc == Instruction::SExt && ShiftOpc == Instruction::AShr)) {
7188+
Value *SLTZero =
7189+
Builder.CreateICmpSLT(X, Constant::getNullValue(X->getType()));
7190+
Value *Cmp = Builder.CreateICmp(Pred, SLTZero, Y, I.getName());
7191+
return replaceInstUsesWith(I, Cmp);
7192+
}
7193+
}
7194+
}
71977195
}
71987196

71997197
if (Instruction *Res = foldICmpEquality(I))

‎llvm/test/Transforms/InstCombine/icmp-shr.ll

Lines changed: 118 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1302,9 +1302,9 @@ define i1 @lshr_neg_sgt_zero(i8 %x) {
13021302

13031303
define i1 @exactly_one_set_signbit(i8 %x, i8 %y) {
13041304
; CHECK-LABEL: @exactly_one_set_signbit(
1305-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor i8 [[X:%.*]], [[Y:%.*]]
1306-
; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[XOR_SIGNBITS]], 0
1307-
; CHECK-NEXT: ret i1 [[R]]
1305+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[X:%.*]], [[Y:%.*]]
1306+
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i8 [[TMP1]], 0
1307+
; CHECK-NEXT: ret i1 [[TMP2]]
13081308
;
13091309
%xsign = lshr i8 %x, 7
13101310
%ypos = icmp sgt i8 %y, -1
@@ -1317,9 +1317,9 @@ define i1 @exactly_one_set_signbit_use1(i8 %x, i8 %y) {
13171317
; CHECK-LABEL: @exactly_one_set_signbit_use1(
13181318
; CHECK-NEXT: [[XSIGN:%.*]] = lshr i8 [[X:%.*]], 7
13191319
; CHECK-NEXT: call void @use(i8 [[XSIGN]])
1320-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor i8 [[X]], [[Y:%.*]]
1321-
; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[XOR_SIGNBITS]], 0
1322-
; CHECK-NEXT: ret i1 [[R]]
1320+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[X]], [[Y:%.*]]
1321+
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i8 [[TMP1]], 0
1322+
; CHECK-NEXT: ret i1 [[TMP2]]
13231323
;
13241324
%xsign = lshr i8 %x, 7
13251325
call void @use(i8 %xsign)
@@ -1331,9 +1331,9 @@ define i1 @exactly_one_set_signbit_use1(i8 %x, i8 %y) {
13311331

13321332
define <2 x i1> @same_signbit(<2 x i8> %x, <2 x i8> %y) {
13331333
; CHECK-LABEL: @same_signbit(
1334-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
1335-
; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i8> [[XOR_SIGNBITS]], <i8 -1, i8 -1>
1336-
; CHECK-NEXT: ret <2 x i1> [[R]]
1334+
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
1335+
; CHECK-NEXT: [[R1:%.*]] = icmp sgt <2 x i8> [[TMP1]], <i8 -1, i8 -1>
1336+
; CHECK-NEXT: ret <2 x i1> [[R1]]
13371337
;
13381338
%xsign = lshr <2 x i8> %x, <i8 7, i8 7>
13391339
%ypos = icmp sgt <2 x i8> %y, <i8 -1, i8 -1>
@@ -1347,9 +1347,9 @@ define i1 @same_signbit_use2(i8 %x, i8 %y) {
13471347
; CHECK-NEXT: [[YPOS:%.*]] = icmp sgt i8 [[Y:%.*]], -1
13481348
; CHECK-NEXT: [[YPOSZ:%.*]] = zext i1 [[YPOS]] to i8
13491349
; CHECK-NEXT: call void @use(i8 [[YPOSZ]])
1350-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor i8 [[X:%.*]], [[Y]]
1351-
; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[XOR_SIGNBITS]], -1
1352-
; CHECK-NEXT: ret i1 [[R]]
1350+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[X:%.*]], [[Y]]
1351+
; CHECK-NEXT: [[R1:%.*]] = icmp sgt i8 [[TMP1]], -1
1352+
; CHECK-NEXT: ret i1 [[R1]]
13531353
;
13541354
%xsign = lshr i8 %x, 7
13551355
%ypos = icmp sgt i8 %y, -1
@@ -1382,9 +1382,10 @@ define i1 @same_signbit_use3(i8 %x, i8 %y) {
13821382

13831383
define <2 x i1> @same_signbit_poison_elts(<2 x i8> %x, <2 x i8> %y) {
13841384
; CHECK-LABEL: @same_signbit_poison_elts(
1385-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
1386-
; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i8> [[XOR_SIGNBITS]], <i8 -1, i8 -1>
1387-
; CHECK-NEXT: ret <2 x i1> [[R]]
1385+
; CHECK-NEXT: [[YPOS:%.*]] = icmp sgt <2 x i8> [[Y:%.*]], <i8 -1, i8 poison>
1386+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
1387+
; CHECK-NEXT: [[R1:%.*]] = xor <2 x i1> [[TMP1]], [[YPOS]]
1388+
; CHECK-NEXT: ret <2 x i1> [[R1]]
13881389
;
13891390
%xsign = lshr <2 x i8> %x, <i8 7, i8 poison>
13901391
%ypos = icmp sgt <2 x i8> %y, <i8 -1, i8 poison>
@@ -1397,11 +1398,10 @@ define <2 x i1> @same_signbit_poison_elts(<2 x i8> %x, <2 x i8> %y) {
13971398

13981399
define i1 @same_signbit_wrong_type(i8 %x, i32 %y) {
13991400
; CHECK-LABEL: @same_signbit_wrong_type(
1400-
; CHECK-NEXT: [[XSIGN:%.*]] = lshr i8 [[X:%.*]], 7
14011401
; CHECK-NEXT: [[YPOS:%.*]] = icmp sgt i32 [[Y:%.*]], -1
1402-
; CHECK-NEXT: [[YPOSZ:%.*]] = zext i1 [[YPOS]] to i8
1403-
; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[XSIGN]], [[YPOSZ]]
1404-
; CHECK-NEXT: ret i1 [[R]]
1402+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[X:%.*]], 0
1403+
; CHECK-NEXT: [[R1:%.*]] = xor i1 [[TMP1]], [[YPOS]]
1404+
; CHECK-NEXT: ret i1 [[R1]]
14051405
;
14061406
%xsign = lshr i8 %x, 7
14071407
%ypos = icmp sgt i32 %y, -1
@@ -1450,11 +1450,9 @@ define i1 @exactly_one_set_signbit_wrong_shr(i8 %x, i8 %y) {
14501450

14511451
define i1 @exactly_one_set_signbit_wrong_pred(i8 %x, i8 %y) {
14521452
; CHECK-LABEL: @exactly_one_set_signbit_wrong_pred(
1453-
; CHECK-NEXT: [[XSIGN:%.*]] = lshr i8 [[X:%.*]], 7
1454-
; CHECK-NEXT: [[YPOS:%.*]] = icmp sgt i8 [[Y:%.*]], -1
1455-
; CHECK-NEXT: [[YPOSZ:%.*]] = zext i1 [[YPOS]] to i8
1456-
; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[XSIGN]], [[YPOSZ]]
1457-
; CHECK-NEXT: ret i1 [[R]]
1453+
; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[Y:%.*]], [[X:%.*]]
1454+
; CHECK-NEXT: [[R1:%.*]] = icmp slt i8 [[TMP1]], 0
1455+
; CHECK-NEXT: ret i1 [[R1]]
14581456
;
14591457
%xsign = lshr i8 %x, 7
14601458
%ypos = icmp sgt i8 %y, -1
@@ -1465,9 +1463,9 @@ define i1 @exactly_one_set_signbit_wrong_pred(i8 %x, i8 %y) {
14651463

14661464
define i1 @exactly_one_set_signbit_signed(i8 %x, i8 %y) {
14671465
; CHECK-LABEL: @exactly_one_set_signbit_signed(
1468-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor i8 [[X:%.*]], [[Y:%.*]]
1469-
; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[XOR_SIGNBITS]], 0
1470-
; CHECK-NEXT: ret i1 [[R]]
1466+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[X:%.*]], [[Y:%.*]]
1467+
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i8 [[TMP1]], 0
1468+
; CHECK-NEXT: ret i1 [[TMP2]]
14711469
;
14721470
%xsign = ashr i8 %x, 7
14731471
%ypos = icmp sgt i8 %y, -1
@@ -1480,9 +1478,9 @@ define i1 @exactly_one_set_signbit_use1_signed(i8 %x, i8 %y) {
14801478
; CHECK-LABEL: @exactly_one_set_signbit_use1_signed(
14811479
; CHECK-NEXT: [[XSIGN:%.*]] = ashr i8 [[X:%.*]], 7
14821480
; CHECK-NEXT: call void @use(i8 [[XSIGN]])
1483-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor i8 [[X]], [[Y:%.*]]
1484-
; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[XOR_SIGNBITS]], 0
1485-
; CHECK-NEXT: ret i1 [[R]]
1481+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[X]], [[Y:%.*]]
1482+
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt i8 [[TMP1]], 0
1483+
; CHECK-NEXT: ret i1 [[TMP2]]
14861484
;
14871485
%xsign = ashr i8 %x, 7
14881486
call void @use(i8 %xsign)
@@ -1494,9 +1492,9 @@ define i1 @exactly_one_set_signbit_use1_signed(i8 %x, i8 %y) {
14941492

14951493
define <2 x i1> @same_signbit_signed(<2 x i8> %x, <2 x i8> %y) {
14961494
; CHECK-LABEL: @same_signbit_signed(
1497-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
1498-
; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i8> [[XOR_SIGNBITS]], <i8 -1, i8 -1>
1499-
; CHECK-NEXT: ret <2 x i1> [[R]]
1495+
; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
1496+
; CHECK-NEXT: [[R1:%.*]] = icmp sgt <2 x i8> [[TMP1]], <i8 -1, i8 -1>
1497+
; CHECK-NEXT: ret <2 x i1> [[R1]]
15001498
;
15011499
%xsign = ashr <2 x i8> %x, <i8 7, i8 7>
15021500
%ypos = icmp sgt <2 x i8> %y, <i8 -1, i8 -1>
@@ -1510,9 +1508,9 @@ define i1 @same_signbit_use2_signed(i8 %x, i8 %y) {
15101508
; CHECK-NEXT: [[YPOS:%.*]] = icmp sgt i8 [[Y:%.*]], -1
15111509
; CHECK-NEXT: [[YPOSZ:%.*]] = sext i1 [[YPOS]] to i8
15121510
; CHECK-NEXT: call void @use(i8 [[YPOSZ]])
1513-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor i8 [[X:%.*]], [[Y]]
1514-
; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[XOR_SIGNBITS]], -1
1515-
; CHECK-NEXT: ret i1 [[R]]
1511+
; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[X:%.*]], [[Y]]
1512+
; CHECK-NEXT: [[R1:%.*]] = icmp sgt i8 [[TMP1]], -1
1513+
; CHECK-NEXT: ret i1 [[R1]]
15161514
;
15171515
%xsign = ashr i8 %x, 7
15181516
%ypos = icmp sgt i8 %y, -1
@@ -1545,9 +1543,10 @@ define i1 @same_signbit_use3_signed(i8 %x, i8 %y) {
15451543

15461544
define <2 x i1> @same_signbit_poison_elts_signed(<2 x i8> %x, <2 x i8> %y) {
15471545
; CHECK-LABEL: @same_signbit_poison_elts_signed(
1548-
; CHECK-NEXT: [[XOR_SIGNBITS:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
1549-
; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i8> [[XOR_SIGNBITS]], <i8 -1, i8 -1>
1550-
; CHECK-NEXT: ret <2 x i1> [[R]]
1546+
; CHECK-NEXT: [[YPOS:%.*]] = icmp sgt <2 x i8> [[Y:%.*]], <i8 -1, i8 poison>
1547+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i8> [[X:%.*]], zeroinitializer
1548+
; CHECK-NEXT: [[R1:%.*]] = xor <2 x i1> [[TMP1]], [[YPOS]]
1549+
; CHECK-NEXT: ret <2 x i1> [[R1]]
15511550
;
15521551
%xsign = ashr <2 x i8> %x, <i8 7, i8 poison>
15531552
%ypos = icmp sgt <2 x i8> %y, <i8 -1, i8 poison>
@@ -1560,11 +1559,10 @@ define <2 x i1> @same_signbit_poison_elts_signed(<2 x i8> %x, <2 x i8> %y) {
15601559

15611560
define i1 @same_signbit_wrong_type_signed(i8 %x, i32 %y) {
15621561
; CHECK-LABEL: @same_signbit_wrong_type_signed(
1563-
; CHECK-NEXT: [[XSIGN:%.*]] = ashr i8 [[X:%.*]], 7
15641562
; CHECK-NEXT: [[YPOS:%.*]] = icmp sgt i32 [[Y:%.*]], -1
1565-
; CHECK-NEXT: [[YPOSZ:%.*]] = sext i1 [[YPOS]] to i8
1566-
; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[XSIGN]], [[YPOSZ]]
1567-
; CHECK-NEXT: ret i1 [[R]]
1563+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i8 [[X:%.*]], 0
1564+
; CHECK-NEXT: [[R1:%.*]] = xor i1 [[TMP1]], [[YPOS]]
1565+
; CHECK-NEXT: ret i1 [[R1]]
15681566
;
15691567
%xsign = ashr i8 %x, 7
15701568
%ypos = icmp sgt i32 %y, -1
@@ -1589,3 +1587,80 @@ define i1 @exactly_one_set_signbit_wrong_shamt_signed(i8 %x, i8 %y) {
15891587
%r = icmp eq i8 %xsign, %yposz
15901588
ret i1 %r
15911589
}
1590+
1591+
define i1 @slt_zero_ult_i1(i32 %a, i1 %b) {
1592+
; CHECK-LABEL: @slt_zero_ult_i1(
1593+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
1594+
; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[B:%.*]], true
1595+
; CHECK-NEXT: [[CMP21:%.*]] = and i1 [[TMP1]], [[TMP2]]
1596+
; CHECK-NEXT: ret i1 [[CMP21]]
1597+
;
1598+
%conv = zext i1 %b to i32
1599+
%cmp1 = lshr i32 %a, 31
1600+
%cmp2 = icmp ult i32 %conv, %cmp1
1601+
ret i1 %cmp2
1602+
}
1603+
1604+
define i1 @slt_zero_ult_i1_fail1(i32 %a, i1 %b) {
1605+
; CHECK-LABEL: @slt_zero_ult_i1_fail1(
1606+
; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[B:%.*]] to i32
1607+
; CHECK-NEXT: [[CMP1:%.*]] = lshr i32 [[A:%.*]], 30
1608+
; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i32 [[CMP1]], [[CONV]]
1609+
; CHECK-NEXT: ret i1 [[CMP2]]
1610+
;
1611+
%conv = zext i1 %b to i32
1612+
%cmp1 = lshr i32 %a, 30
1613+
%cmp2 = icmp ult i32 %conv, %cmp1
1614+
ret i1 %cmp2
1615+
}
1616+
1617+
define i1 @slt_zero_ult_i1_fail2(i32 %a, i1 %b) {
1618+
; CHECK-LABEL: @slt_zero_ult_i1_fail2(
1619+
; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[B:%.*]] to i32
1620+
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[A:%.*]], 31
1621+
; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i32 [[CMP1]], [[CONV]]
1622+
; CHECK-NEXT: ret i1 [[CMP2]]
1623+
;
1624+
%conv = zext i1 %b to i32
1625+
%cmp1 = ashr i32 %a, 31
1626+
%cmp2 = icmp ult i32 %conv, %cmp1
1627+
ret i1 %cmp2
1628+
}
1629+
1630+
define i1 @slt_zero_slt_i1_fail(i32 %a, i1 %b) {
1631+
; CHECK-LABEL: @slt_zero_slt_i1_fail(
1632+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[A:%.*]], 0
1633+
; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[B:%.*]], true
1634+
; CHECK-NEXT: [[CMP21:%.*]] = and i1 [[TMP1]], [[TMP2]]
1635+
; CHECK-NEXT: ret i1 [[CMP21]]
1636+
;
1637+
%conv = zext i1 %b to i32
1638+
%cmp1 = lshr i32 %a, 31
1639+
%cmp2 = icmp slt i32 %conv, %cmp1
1640+
ret i1 %cmp2
1641+
}
1642+
1643+
define i1 @slt_zero_eq_i1_signed(i32 %a, i1 %b) {
1644+
; CHECK-LABEL: @slt_zero_eq_i1_signed(
1645+
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[A:%.*]], -1
1646+
; CHECK-NEXT: [[CMP21:%.*]] = xor i1 [[TMP1]], [[B:%.*]]
1647+
; CHECK-NEXT: ret i1 [[CMP21]]
1648+
;
1649+
%conv = sext i1 %b to i32
1650+
%cmp1 = ashr i32 %a, 31
1651+
%cmp2 = icmp eq i32 %conv, %cmp1
1652+
ret i1 %cmp2
1653+
}
1654+
1655+
define i1 @slt_zero_eq_i1_fail_signed(i32 %a, i1 %b) {
1656+
; CHECK-LABEL: @slt_zero_eq_i1_fail_signed(
1657+
; CHECK-NEXT: [[CONV:%.*]] = sext i1 [[B:%.*]] to i32
1658+
; CHECK-NEXT: [[CMP1:%.*]] = lshr i32 [[A:%.*]], 31
1659+
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[CMP1]], [[CONV]]
1660+
; CHECK-NEXT: ret i1 [[CMP2]]
1661+
;
1662+
%conv = sext i1 %b to i32
1663+
%cmp1 = lshr i32 %a, 31
1664+
%cmp2 = icmp eq i32 %conv, %cmp1
1665+
ret i1 %cmp2
1666+
}

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