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[RISCV] Correct Zhinx load/store patterns to use AddrRegImm.
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5 files changed

+177
-297
lines changed

5 files changed

+177
-297
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -425,11 +425,13 @@ def : StPat<store, FSH, FPR16, f16>;
425425

426426
let Predicates = [HasStdExtZhinxOrZhinxmin] in {
427427
/// Loads
428-
def : Pat<(f16 (load GPR:$rs1)), (COPY_TO_REGCLASS (LH GPR:$rs1, 0), GPRF16)>;
428+
def : Pat<(f16 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
429+
(COPY_TO_REGCLASS (LH GPR:$rs1, simm12:$imm12), GPRF16)>;
429430

430431
/// Stores
431-
def : Pat<(store (f16 FPR16INX:$rs2), GPR:$rs1),
432-
(SH (COPY_TO_REGCLASS FPR16INX:$rs2, GPR), GPR:$rs1, 0)>;
432+
def : Pat<(store (f16 FPR16INX:$rs2),
433+
(AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
434+
(SH (COPY_TO_REGCLASS FPR16INX:$rs2, GPR), GPR:$rs1, simm12:$imm12)>;
433435
} // Predicates = [HasStdExtZhinxOrZhinxmin]
434436

435437
let Predicates = [HasStdExtZfhOrZfhmin] in {

‎llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll

Lines changed: 119 additions & 207 deletions
Original file line numberDiff line numberDiff line change
@@ -270,101 +270,57 @@ define half @caller_half_32(<32 x half> %A) nounwind {
270270
; ZHINX32-NEXT: sw s9, 68(sp) # 4-byte Folded Spill
271271
; ZHINX32-NEXT: sw s10, 64(sp) # 4-byte Folded Spill
272272
; ZHINX32-NEXT: sw s11, 60(sp) # 4-byte Folded Spill
273-
; ZHINX32-NEXT: addi t0, sp, 112
274-
; ZHINX32-NEXT: lh t0, 0(t0)
273+
; ZHINX32-NEXT: lh t0, 112(sp)
275274
; ZHINX32-NEXT: sw t0, 56(sp) # 4-byte Folded Spill
276-
; ZHINX32-NEXT: addi t0, sp, 116
277-
; ZHINX32-NEXT: lh t0, 0(t0)
275+
; ZHINX32-NEXT: lh t0, 116(sp)
278276
; ZHINX32-NEXT: sw t0, 52(sp) # 4-byte Folded Spill
279-
; ZHINX32-NEXT: addi t0, sp, 120
280-
; ZHINX32-NEXT: lh t0, 0(t0)
277+
; ZHINX32-NEXT: lh t0, 120(sp)
281278
; ZHINX32-NEXT: sw t0, 48(sp) # 4-byte Folded Spill
282-
; ZHINX32-NEXT: addi t0, sp, 124
283-
; ZHINX32-NEXT: lh t0, 0(t0)
279+
; ZHINX32-NEXT: lh t0, 124(sp)
284280
; ZHINX32-NEXT: sw t0, 44(sp) # 4-byte Folded Spill
285-
; ZHINX32-NEXT: addi t0, sp, 128
286-
; ZHINX32-NEXT: lh t0, 0(t0)
287-
; ZHINX32-NEXT: sw t0, 40(sp) # 4-byte Folded Spill
288-
; ZHINX32-NEXT: addi t0, sp, 132
289-
; ZHINX32-NEXT: lh t6, 0(t0)
290-
; ZHINX32-NEXT: addi t1, sp, 136
291-
; ZHINX32-NEXT: lh t1, 0(t1)
292-
; ZHINX32-NEXT: addi s0, sp, 140
293-
; ZHINX32-NEXT: lh s0, 0(s0)
294-
; ZHINX32-NEXT: addi s1, sp, 144
295-
; ZHINX32-NEXT: lh s1, 0(s1)
296-
; ZHINX32-NEXT: addi s2, sp, 148
297-
; ZHINX32-NEXT: lh s2, 0(s2)
298-
; ZHINX32-NEXT: addi s3, sp, 152
299-
; ZHINX32-NEXT: lh s3, 0(s3)
300-
; ZHINX32-NEXT: addi s4, sp, 156
301-
; ZHINX32-NEXT: lh s4, 0(s4)
302-
; ZHINX32-NEXT: addi s5, sp, 160
303-
; ZHINX32-NEXT: lh s5, 0(s5)
304-
; ZHINX32-NEXT: addi s6, sp, 164
305-
; ZHINX32-NEXT: lh s6, 0(s6)
306-
; ZHINX32-NEXT: addi s7, sp, 168
307-
; ZHINX32-NEXT: lh s7, 0(s7)
308-
; ZHINX32-NEXT: addi s8, sp, 172
309-
; ZHINX32-NEXT: lh s8, 0(s8)
310-
; ZHINX32-NEXT: addi s9, sp, 176
311-
; ZHINX32-NEXT: lh s9, 0(s9)
312-
; ZHINX32-NEXT: addi s10, sp, 180
313-
; ZHINX32-NEXT: lh s10, 0(s10)
314-
; ZHINX32-NEXT: addi s11, sp, 184
315-
; ZHINX32-NEXT: lh s11, 0(s11)
316-
; ZHINX32-NEXT: addi ra, sp, 188
317-
; ZHINX32-NEXT: lh ra, 0(ra)
318-
; ZHINX32-NEXT: addi t0, sp, 192
319-
; ZHINX32-NEXT: lh t0, 0(t0)
320-
; ZHINX32-NEXT: addi t2, sp, 196
321-
; ZHINX32-NEXT: lh t2, 0(t2)
322-
; ZHINX32-NEXT: addi t3, sp, 200
323-
; ZHINX32-NEXT: lh t3, 0(t3)
324-
; ZHINX32-NEXT: addi t4, sp, 204
325-
; ZHINX32-NEXT: lh t4, 0(t4)
326-
; ZHINX32-NEXT: addi t5, sp, 36
327-
; ZHINX32-NEXT: sh t4, 0(t5)
328-
; ZHINX32-NEXT: addi t4, sp, 34
329-
; ZHINX32-NEXT: sh t3, 0(t4)
330-
; ZHINX32-NEXT: addi t3, sp, 32
331-
; ZHINX32-NEXT: sh t2, 0(t3)
332-
; ZHINX32-NEXT: addi t2, sp, 30
333-
; ZHINX32-NEXT: sh t0, 0(t2)
334-
; ZHINX32-NEXT: addi t0, sp, 28
335-
; ZHINX32-NEXT: sh ra, 0(t0)
336-
; ZHINX32-NEXT: addi t0, sp, 26
337-
; ZHINX32-NEXT: sh s11, 0(t0)
338-
; ZHINX32-NEXT: addi t0, sp, 24
339-
; ZHINX32-NEXT: sh s10, 0(t0)
340-
; ZHINX32-NEXT: addi t0, sp, 22
341-
; ZHINX32-NEXT: sh s9, 0(t0)
342-
; ZHINX32-NEXT: addi t0, sp, 20
343-
; ZHINX32-NEXT: sh s8, 0(t0)
344-
; ZHINX32-NEXT: addi t0, sp, 18
345-
; ZHINX32-NEXT: sh s7, 0(t0)
346-
; ZHINX32-NEXT: addi t0, sp, 16
347-
; ZHINX32-NEXT: sh s6, 0(t0)
348-
; ZHINX32-NEXT: addi t0, sp, 14
349-
; ZHINX32-NEXT: sh s5, 0(t0)
350-
; ZHINX32-NEXT: addi t0, sp, 12
351-
; ZHINX32-NEXT: sh s4, 0(t0)
352-
; ZHINX32-NEXT: addi t0, sp, 10
353-
; ZHINX32-NEXT: sh s3, 0(t0)
354-
; ZHINX32-NEXT: addi t0, sp, 8
355-
; ZHINX32-NEXT: sh s2, 0(t0)
356-
; ZHINX32-NEXT: addi t0, sp, 6
357-
; ZHINX32-NEXT: sh s1, 0(t0)
358-
; ZHINX32-NEXT: addi t0, sp, 4
359-
; ZHINX32-NEXT: sh s0, 0(t0)
360-
; ZHINX32-NEXT: addi t0, sp, 2
361-
; ZHINX32-NEXT: sh t1, 0(t0)
362-
; ZHINX32-NEXT: sh t6, 0(sp)
281+
; ZHINX32-NEXT: lh t6, 128(sp)
282+
; ZHINX32-NEXT: lh t5, 132(sp)
283+
; ZHINX32-NEXT: lh t4, 136(sp)
284+
; ZHINX32-NEXT: lh s0, 140(sp)
285+
; ZHINX32-NEXT: lh s1, 144(sp)
286+
; ZHINX32-NEXT: lh s2, 148(sp)
287+
; ZHINX32-NEXT: lh s3, 152(sp)
288+
; ZHINX32-NEXT: lh s4, 156(sp)
289+
; ZHINX32-NEXT: lh s5, 160(sp)
290+
; ZHINX32-NEXT: lh s6, 164(sp)
291+
; ZHINX32-NEXT: lh s7, 168(sp)
292+
; ZHINX32-NEXT: lh s8, 172(sp)
293+
; ZHINX32-NEXT: lh s9, 176(sp)
294+
; ZHINX32-NEXT: lh s10, 180(sp)
295+
; ZHINX32-NEXT: lh s11, 184(sp)
296+
; ZHINX32-NEXT: lh ra, 188(sp)
297+
; ZHINX32-NEXT: lh t3, 192(sp)
298+
; ZHINX32-NEXT: lh t2, 196(sp)
299+
; ZHINX32-NEXT: lh t1, 200(sp)
300+
; ZHINX32-NEXT: lh t0, 204(sp)
301+
; ZHINX32-NEXT: sh t0, 36(sp)
302+
; ZHINX32-NEXT: sh t1, 34(sp)
303+
; ZHINX32-NEXT: sh t2, 32(sp)
304+
; ZHINX32-NEXT: sh t3, 30(sp)
305+
; ZHINX32-NEXT: sh ra, 28(sp)
306+
; ZHINX32-NEXT: sh s11, 26(sp)
307+
; ZHINX32-NEXT: sh s10, 24(sp)
308+
; ZHINX32-NEXT: sh s9, 22(sp)
309+
; ZHINX32-NEXT: sh s8, 20(sp)
310+
; ZHINX32-NEXT: sh s7, 18(sp)
311+
; ZHINX32-NEXT: sh s6, 16(sp)
312+
; ZHINX32-NEXT: sh s5, 14(sp)
313+
; ZHINX32-NEXT: sh s4, 12(sp)
314+
; ZHINX32-NEXT: sh s3, 10(sp)
315+
; ZHINX32-NEXT: sh s2, 8(sp)
316+
; ZHINX32-NEXT: sh s1, 6(sp)
317+
; ZHINX32-NEXT: sh s0, 4(sp)
318+
; ZHINX32-NEXT: sh t4, 2(sp)
319+
; ZHINX32-NEXT: sh t5, 0(sp)
363320
; ZHINX32-NEXT: lw t2, 56(sp) # 4-byte Folded Reload
364321
; ZHINX32-NEXT: lw t3, 52(sp) # 4-byte Folded Reload
365322
; ZHINX32-NEXT: lw t4, 48(sp) # 4-byte Folded Reload
366323
; ZHINX32-NEXT: lw t5, 44(sp) # 4-byte Folded Reload
367-
; ZHINX32-NEXT: lw t6, 40(sp) # 4-byte Folded Reload
368324
; ZHINX32-NEXT: call callee_half_32@plt
369325
; ZHINX32-NEXT: lw ra, 108(sp) # 4-byte Folded Reload
370326
; ZHINX32-NEXT: lw s0, 104(sp) # 4-byte Folded Reload
@@ -384,130 +340,86 @@ define half @caller_half_32(<32 x half> %A) nounwind {
384340
;
385341
; ZHINX64-LABEL: caller_half_32:
386342
; ZHINX64: # %bb.0:
387-
; ZHINX64-NEXT: addi sp, sp, -192
388-
; ZHINX64-NEXT: sd ra, 184(sp) # 8-byte Folded Spill
389-
; ZHINX64-NEXT: sd s0, 176(sp) # 8-byte Folded Spill
390-
; ZHINX64-NEXT: sd s1, 168(sp) # 8-byte Folded Spill
391-
; ZHINX64-NEXT: sd s2, 160(sp) # 8-byte Folded Spill
392-
; ZHINX64-NEXT: sd s3, 152(sp) # 8-byte Folded Spill
393-
; ZHINX64-NEXT: sd s4, 144(sp) # 8-byte Folded Spill
394-
; ZHINX64-NEXT: sd s5, 136(sp) # 8-byte Folded Spill
395-
; ZHINX64-NEXT: sd s6, 128(sp) # 8-byte Folded Spill
396-
; ZHINX64-NEXT: sd s7, 120(sp) # 8-byte Folded Spill
397-
; ZHINX64-NEXT: sd s8, 112(sp) # 8-byte Folded Spill
398-
; ZHINX64-NEXT: sd s9, 104(sp) # 8-byte Folded Spill
399-
; ZHINX64-NEXT: sd s10, 96(sp) # 8-byte Folded Spill
400-
; ZHINX64-NEXT: sd s11, 88(sp) # 8-byte Folded Spill
401-
; ZHINX64-NEXT: addi t0, sp, 192
402-
; ZHINX64-NEXT: lh t0, 0(t0)
403-
; ZHINX64-NEXT: sd t0, 80(sp) # 8-byte Folded Spill
404-
; ZHINX64-NEXT: addi t0, sp, 200
405-
; ZHINX64-NEXT: lh t0, 0(t0)
406-
; ZHINX64-NEXT: sd t0, 72(sp) # 8-byte Folded Spill
407-
; ZHINX64-NEXT: addi t0, sp, 208
408-
; ZHINX64-NEXT: lh t0, 0(t0)
343+
; ZHINX64-NEXT: addi sp, sp, -176
344+
; ZHINX64-NEXT: sd ra, 168(sp) # 8-byte Folded Spill
345+
; ZHINX64-NEXT: sd s0, 160(sp) # 8-byte Folded Spill
346+
; ZHINX64-NEXT: sd s1, 152(sp) # 8-byte Folded Spill
347+
; ZHINX64-NEXT: sd s2, 144(sp) # 8-byte Folded Spill
348+
; ZHINX64-NEXT: sd s3, 136(sp) # 8-byte Folded Spill
349+
; ZHINX64-NEXT: sd s4, 128(sp) # 8-byte Folded Spill
350+
; ZHINX64-NEXT: sd s5, 120(sp) # 8-byte Folded Spill
351+
; ZHINX64-NEXT: sd s6, 112(sp) # 8-byte Folded Spill
352+
; ZHINX64-NEXT: sd s7, 104(sp) # 8-byte Folded Spill
353+
; ZHINX64-NEXT: sd s8, 96(sp) # 8-byte Folded Spill
354+
; ZHINX64-NEXT: sd s9, 88(sp) # 8-byte Folded Spill
355+
; ZHINX64-NEXT: sd s10, 80(sp) # 8-byte Folded Spill
356+
; ZHINX64-NEXT: sd s11, 72(sp) # 8-byte Folded Spill
357+
; ZHINX64-NEXT: lh t0, 176(sp)
409358
; ZHINX64-NEXT: sd t0, 64(sp) # 8-byte Folded Spill
410-
; ZHINX64-NEXT: addi t0, sp, 216
411-
; ZHINX64-NEXT: lh t0, 0(t0)
359+
; ZHINX64-NEXT: lh t0, 184(sp)
412360
; ZHINX64-NEXT: sd t0, 56(sp) # 8-byte Folded Spill
413-
; ZHINX64-NEXT: addi t0, sp, 224
414-
; ZHINX64-NEXT: lh t0, 0(t0)
361+
; ZHINX64-NEXT: lh t0, 192(sp)
415362
; ZHINX64-NEXT: sd t0, 48(sp) # 8-byte Folded Spill
416-
; ZHINX64-NEXT: addi t0, sp, 232
417-
; ZHINX64-NEXT: lh t6, 0(t0)
418-
; ZHINX64-NEXT: addi t1, sp, 240
419-
; ZHINX64-NEXT: lh t1, 0(t1)
420-
; ZHINX64-NEXT: addi s0, sp, 248
421-
; ZHINX64-NEXT: lh s0, 0(s0)
422-
; ZHINX64-NEXT: addi s1, sp, 256
423-
; ZHINX64-NEXT: lh s1, 0(s1)
424-
; ZHINX64-NEXT: addi s2, sp, 264
425-
; ZHINX64-NEXT: lh s2, 0(s2)
426-
; ZHINX64-NEXT: addi s3, sp, 272
427-
; ZHINX64-NEXT: lh s3, 0(s3)
428-
; ZHINX64-NEXT: addi s4, sp, 280
429-
; ZHINX64-NEXT: lh s4, 0(s4)
430-
; ZHINX64-NEXT: addi s5, sp, 288
431-
; ZHINX64-NEXT: lh s5, 0(s5)
432-
; ZHINX64-NEXT: addi s6, sp, 296
433-
; ZHINX64-NEXT: lh s6, 0(s6)
434-
; ZHINX64-NEXT: addi s7, sp, 304
435-
; ZHINX64-NEXT: lh s7, 0(s7)
436-
; ZHINX64-NEXT: addi s8, sp, 312
437-
; ZHINX64-NEXT: lh s8, 0(s8)
438-
; ZHINX64-NEXT: addi s9, sp, 320
439-
; ZHINX64-NEXT: lh s9, 0(s9)
440-
; ZHINX64-NEXT: addi s10, sp, 328
441-
; ZHINX64-NEXT: lh s10, 0(s10)
442-
; ZHINX64-NEXT: addi s11, sp, 336
443-
; ZHINX64-NEXT: lh s11, 0(s11)
444-
; ZHINX64-NEXT: addi ra, sp, 344
445-
; ZHINX64-NEXT: lh ra, 0(ra)
446-
; ZHINX64-NEXT: addi t0, sp, 352
447-
; ZHINX64-NEXT: lh t0, 0(t0)
448-
; ZHINX64-NEXT: addi t2, sp, 360
449-
; ZHINX64-NEXT: lh t2, 0(t2)
450-
; ZHINX64-NEXT: addi t3, sp, 368
451-
; ZHINX64-NEXT: lh t3, 0(t3)
452-
; ZHINX64-NEXT: addi t4, sp, 376
453-
; ZHINX64-NEXT: lh t4, 0(t4)
454-
; ZHINX64-NEXT: addi t5, sp, 36
455-
; ZHINX64-NEXT: sh t4, 0(t5)
456-
; ZHINX64-NEXT: addi t4, sp, 34
457-
; ZHINX64-NEXT: sh t3, 0(t4)
458-
; ZHINX64-NEXT: addi t3, sp, 32
459-
; ZHINX64-NEXT: sh t2, 0(t3)
460-
; ZHINX64-NEXT: addi t2, sp, 30
461-
; ZHINX64-NEXT: sh t0, 0(t2)
462-
; ZHINX64-NEXT: addi t0, sp, 28
463-
; ZHINX64-NEXT: sh ra, 0(t0)
464-
; ZHINX64-NEXT: addi t0, sp, 26
465-
; ZHINX64-NEXT: sh s11, 0(t0)
466-
; ZHINX64-NEXT: addi t0, sp, 24
467-
; ZHINX64-NEXT: sh s10, 0(t0)
468-
; ZHINX64-NEXT: addi t0, sp, 22
469-
; ZHINX64-NEXT: sh s9, 0(t0)
470-
; ZHINX64-NEXT: addi t0, sp, 20
471-
; ZHINX64-NEXT: sh s8, 0(t0)
472-
; ZHINX64-NEXT: addi t0, sp, 18
473-
; ZHINX64-NEXT: sh s7, 0(t0)
474-
; ZHINX64-NEXT: addi t0, sp, 16
475-
; ZHINX64-NEXT: sh s6, 0(t0)
476-
; ZHINX64-NEXT: addi t0, sp, 14
477-
; ZHINX64-NEXT: sh s5, 0(t0)
478-
; ZHINX64-NEXT: addi t0, sp, 12
479-
; ZHINX64-NEXT: sh s4, 0(t0)
480-
; ZHINX64-NEXT: addi t0, sp, 10
481-
; ZHINX64-NEXT: sh s3, 0(t0)
482-
; ZHINX64-NEXT: addi t0, sp, 8
483-
; ZHINX64-NEXT: sh s2, 0(t0)
484-
; ZHINX64-NEXT: addi t0, sp, 6
485-
; ZHINX64-NEXT: sh s1, 0(t0)
486-
; ZHINX64-NEXT: addi t0, sp, 4
487-
; ZHINX64-NEXT: sh s0, 0(t0)
488-
; ZHINX64-NEXT: addi t0, sp, 2
489-
; ZHINX64-NEXT: sh t1, 0(t0)
490-
; ZHINX64-NEXT: sh t6, 0(sp)
491-
; ZHINX64-NEXT: ld t2, 80(sp) # 8-byte Folded Reload
492-
; ZHINX64-NEXT: ld t3, 72(sp) # 8-byte Folded Reload
493-
; ZHINX64-NEXT: ld t4, 64(sp) # 8-byte Folded Reload
494-
; ZHINX64-NEXT: ld t5, 56(sp) # 8-byte Folded Reload
495-
; ZHINX64-NEXT: ld t6, 48(sp) # 8-byte Folded Reload
363+
; ZHINX64-NEXT: lh t0, 200(sp)
364+
; ZHINX64-NEXT: sd t0, 40(sp) # 8-byte Folded Spill
365+
; ZHINX64-NEXT: lh t6, 208(sp)
366+
; ZHINX64-NEXT: lh t5, 216(sp)
367+
; ZHINX64-NEXT: lh t4, 224(sp)
368+
; ZHINX64-NEXT: lh s0, 232(sp)
369+
; ZHINX64-NEXT: lh s1, 240(sp)
370+
; ZHINX64-NEXT: lh s2, 248(sp)
371+
; ZHINX64-NEXT: lh s3, 256(sp)
372+
; ZHINX64-NEXT: lh s4, 264(sp)
373+
; ZHINX64-NEXT: lh s5, 272(sp)
374+
; ZHINX64-NEXT: lh s6, 280(sp)
375+
; ZHINX64-NEXT: lh s7, 288(sp)
376+
; ZHINX64-NEXT: lh s8, 296(sp)
377+
; ZHINX64-NEXT: lh s9, 304(sp)
378+
; ZHINX64-NEXT: lh s10, 312(sp)
379+
; ZHINX64-NEXT: lh s11, 320(sp)
380+
; ZHINX64-NEXT: lh ra, 328(sp)
381+
; ZHINX64-NEXT: lh t3, 336(sp)
382+
; ZHINX64-NEXT: lh t2, 344(sp)
383+
; ZHINX64-NEXT: lh t1, 352(sp)
384+
; ZHINX64-NEXT: lh t0, 360(sp)
385+
; ZHINX64-NEXT: sh t0, 36(sp)
386+
; ZHINX64-NEXT: sh t1, 34(sp)
387+
; ZHINX64-NEXT: sh t2, 32(sp)
388+
; ZHINX64-NEXT: sh t3, 30(sp)
389+
; ZHINX64-NEXT: sh ra, 28(sp)
390+
; ZHINX64-NEXT: sh s11, 26(sp)
391+
; ZHINX64-NEXT: sh s10, 24(sp)
392+
; ZHINX64-NEXT: sh s9, 22(sp)
393+
; ZHINX64-NEXT: sh s8, 20(sp)
394+
; ZHINX64-NEXT: sh s7, 18(sp)
395+
; ZHINX64-NEXT: sh s6, 16(sp)
396+
; ZHINX64-NEXT: sh s5, 14(sp)
397+
; ZHINX64-NEXT: sh s4, 12(sp)
398+
; ZHINX64-NEXT: sh s3, 10(sp)
399+
; ZHINX64-NEXT: sh s2, 8(sp)
400+
; ZHINX64-NEXT: sh s1, 6(sp)
401+
; ZHINX64-NEXT: sh s0, 4(sp)
402+
; ZHINX64-NEXT: sh t4, 2(sp)
403+
; ZHINX64-NEXT: sh t5, 0(sp)
404+
; ZHINX64-NEXT: ld t2, 64(sp) # 8-byte Folded Reload
405+
; ZHINX64-NEXT: ld t3, 56(sp) # 8-byte Folded Reload
406+
; ZHINX64-NEXT: ld t4, 48(sp) # 8-byte Folded Reload
407+
; ZHINX64-NEXT: ld t5, 40(sp) # 8-byte Folded Reload
496408
; ZHINX64-NEXT: call callee_half_32@plt
497-
; ZHINX64-NEXT: ld ra, 184(sp) # 8-byte Folded Reload
498-
; ZHINX64-NEXT: ld s0, 176(sp) # 8-byte Folded Reload
499-
; ZHINX64-NEXT: ld s1, 168(sp) # 8-byte Folded Reload
500-
; ZHINX64-NEXT: ld s2, 160(sp) # 8-byte Folded Reload
501-
; ZHINX64-NEXT: ld s3, 152(sp) # 8-byte Folded Reload
502-
; ZHINX64-NEXT: ld s4, 144(sp) # 8-byte Folded Reload
503-
; ZHINX64-NEXT: ld s5, 136(sp) # 8-byte Folded Reload
504-
; ZHINX64-NEXT: ld s6, 128(sp) # 8-byte Folded Reload
505-
; ZHINX64-NEXT: ld s7, 120(sp) # 8-byte Folded Reload
506-
; ZHINX64-NEXT: ld s8, 112(sp) # 8-byte Folded Reload
507-
; ZHINX64-NEXT: ld s9, 104(sp) # 8-byte Folded Reload
508-
; ZHINX64-NEXT: ld s10, 96(sp) # 8-byte Folded Reload
509-
; ZHINX64-NEXT: ld s11, 88(sp) # 8-byte Folded Reload
510-
; ZHINX64-NEXT: addi sp, sp, 192
409+
; ZHINX64-NEXT: ld ra, 168(sp) # 8-byte Folded Reload
410+
; ZHINX64-NEXT: ld s0, 160(sp) # 8-byte Folded Reload
411+
; ZHINX64-NEXT: ld s1, 152(sp) # 8-byte Folded Reload
412+
; ZHINX64-NEXT: ld s2, 144(sp) # 8-byte Folded Reload
413+
; ZHINX64-NEXT: ld s3, 136(sp) # 8-byte Folded Reload
414+
; ZHINX64-NEXT: ld s4, 128(sp) # 8-byte Folded Reload
415+
; ZHINX64-NEXT: ld s5, 120(sp) # 8-byte Folded Reload
416+
; ZHINX64-NEXT: ld s6, 112(sp) # 8-byte Folded Reload
417+
; ZHINX64-NEXT: ld s7, 104(sp) # 8-byte Folded Reload
418+
; ZHINX64-NEXT: ld s8, 96(sp) # 8-byte Folded Reload
419+
; ZHINX64-NEXT: ld s9, 88(sp) # 8-byte Folded Reload
420+
; ZHINX64-NEXT: ld s10, 80(sp) # 8-byte Folded Reload
421+
; ZHINX64-NEXT: ld s11, 72(sp) # 8-byte Folded Reload
422+
; ZHINX64-NEXT: addi sp, sp, 176
511423
; ZHINX64-NEXT: ret
512424
;
513425
; ZFINX32-LABEL: caller_half_32:

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