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AMDGPU: Remove arbitrary SCC liveness scan threshold (#94097)
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2 files changed

+167
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6437,8 +6437,13 @@ loadMBUFScalarOperandsFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,
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// Save SCC. Waterfall Loop may overwrite SCC.
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Register SaveSCCReg;
6440-
bool SCCNotDead = (MBB.computeRegisterLiveness(TRI, AMDGPU::SCC, MI, 30) !=
6441-
MachineBasicBlock::LQR_Dead);
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// FIXME: We should maintain SCC liveness while doing the FixSGPRCopies walk
6442+
// rather than unlimited scan everywhere
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bool SCCNotDead =
6444+
MBB.computeRegisterLiveness(TRI, AMDGPU::SCC, MI,
6445+
std::numeric_limits<unsigned>::max()) !=
6446+
MachineBasicBlock::LQR_Dead;
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if (SCCNotDead) {
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SaveSCCReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
64446449
BuildMI(MBB, Begin, DL, TII.get(AMDGPU::S_CSELECT_B32), SaveSCCReg)

‎llvm/test/CodeGen/AMDGPU/issue92561-restore-undef-scc-verifier-error.ll

Lines changed: 160 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,160 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GISEL %s
4+
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; Check for verifier error due to trying to save and restore SCC
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; around a waterfall looop when it was never defined. We have to get
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; an accurate liveness at the use point and cannot rely on an
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; imprecise maybe-live query.
9+
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define void @issue92561(ptr addrspace(1) %arg) {
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; SDAG-LABEL: issue92561:
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; SDAG: ; %bb.0: ; %bb
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: s_clause 0x1
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; SDAG-NEXT: global_load_b128 v[4:7], v[0:1], off offset:16
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; SDAG-NEXT: global_load_b128 v[0:3], v[0:1], off
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; SDAG-NEXT: v_mov_b32_e32 v8, 0
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; SDAG-NEXT: s_mov_b32 s12, 0
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; SDAG-NEXT: s_mov_b32 s3, exec_lo
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; SDAG-NEXT: s_mov_b32 s13, s12
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; SDAG-NEXT: s_mov_b32 s14, s12
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; SDAG-NEXT: s_mov_b32 s15, s12
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; SDAG-NEXT: s_waitcnt vmcnt(0)
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; SDAG-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
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; SDAG-NEXT: v_readfirstlane_b32 s4, v0
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; SDAG-NEXT: v_readfirstlane_b32 s5, v1
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; SDAG-NEXT: v_readfirstlane_b32 s6, v2
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; SDAG-NEXT: v_readfirstlane_b32 s7, v3
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; SDAG-NEXT: v_readfirstlane_b32 s8, v4
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; SDAG-NEXT: v_readfirstlane_b32 s9, v5
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; SDAG-NEXT: v_readfirstlane_b32 s10, v6
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; SDAG-NEXT: v_readfirstlane_b32 s11, v7
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; SDAG-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
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; SDAG-NEXT: v_cmp_eq_u64_e64 s0, s[6:7], v[2:3]
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; SDAG-NEXT: v_cmp_eq_u64_e64 s1, s[8:9], v[4:5]
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; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
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; SDAG-NEXT: v_cmp_eq_u64_e64 s2, s[10:11], v[6:7]
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; SDAG-NEXT: s_and_b32 s0, vcc_lo, s0
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; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
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; SDAG-NEXT: s_and_b32 s0, s0, s1
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; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
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; SDAG-NEXT: s_and_b32 s0, s0, s2
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; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; SDAG-NEXT: s_and_saveexec_b32 s0, s0
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; SDAG-NEXT: image_sample_c_lz v9, [v8, v8, v8, v8], s[4:11], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
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; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
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; SDAG-NEXT: ; implicit-def: $vgpr8
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; SDAG-NEXT: s_xor_b32 exec_lo, exec_lo, s0
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; SDAG-NEXT: s_cbranch_execnz .LBB0_1
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; SDAG-NEXT: ; %bb.2:
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; SDAG-NEXT: s_mov_b32 exec_lo, s3
52+
; SDAG-NEXT: v_dual_mov_b32 v0, 0x7fc00000 :: v_dual_mov_b32 v1, 0
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; SDAG-NEXT: v_mov_b32_e32 v2, 1.0
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; SDAG-NEXT: s_mov_b32 s0, s12
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; SDAG-NEXT: s_mov_b32 s1, s12
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; SDAG-NEXT: s_mov_b32 s2, s12
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; SDAG-NEXT: s_mov_b32 s3, s12
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; SDAG-NEXT: s_mov_b32 s4, s12
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; SDAG-NEXT: s_mov_b32 s5, s12
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; SDAG-NEXT: s_mov_b32 s6, s12
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; SDAG-NEXT: s_mov_b32 s7, s12
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; SDAG-NEXT: s_clause 0x2
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; SDAG-NEXT: image_sample_c_lz v0, [v1, v1, v0, v1], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
64+
; SDAG-NEXT: image_sample_c_lz v3, [v1, v1, v1, v1], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
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; SDAG-NEXT: image_sample_c_lz v2, [v1, v2, v1, v1], s[0:7], s[12:15] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
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; SDAG-NEXT: v_mov_b32_e32 v4, v1
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; SDAG-NEXT: s_waitcnt vmcnt(2)
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; SDAG-NEXT: v_add_f32_e32 v0, v9, v0
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; SDAG-NEXT: s_waitcnt vmcnt(0)
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; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
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; SDAG-NEXT: v_add_f32_e32 v0, v2, v0
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; SDAG-NEXT: v_mov_b32_e32 v2, v1
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; SDAG-NEXT: v_dual_add_f32 v0, v3, v0 :: v_dual_mov_b32 v3, v1
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; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; SDAG-NEXT: v_mul_f32_e32 v0, 0x3e800000, v0
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; SDAG-NEXT: image_store v[0:2], v[3:4], s[0:7] dim:SQ_RSRC_IMG_2D unorm
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: issue92561:
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; GISEL: ; %bb.0: ; %bb
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; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GISEL-NEXT: s_clause 0x1
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; GISEL-NEXT: global_load_b128 v[2:5], v[0:1], off
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; GISEL-NEXT: global_load_b128 v[6:9], v[0:1], off offset:16
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; GISEL-NEXT: v_mov_b32_e32 v0, 0
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; GISEL-NEXT: s_mov_b32 s20, 0
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; GISEL-NEXT: s_mov_b32 s3, exec_lo
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; GISEL-NEXT: s_mov_b32 s21, s20
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; GISEL-NEXT: s_mov_b32 s22, s20
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; GISEL-NEXT: s_mov_b32 s23, s20
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; GISEL-NEXT: s_mov_b32 s4, s20
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; GISEL-NEXT: s_mov_b32 s5, s20
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; GISEL-NEXT: s_mov_b32 s6, s20
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; GISEL-NEXT: s_mov_b32 s7, s20
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; GISEL-NEXT: s_mov_b32 s8, s20
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; GISEL-NEXT: s_mov_b32 s9, s20
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; GISEL-NEXT: s_mov_b32 s10, s20
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; GISEL-NEXT: s_mov_b32 s11, s20
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; GISEL-NEXT: s_waitcnt vmcnt(0)
100+
; GISEL-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
101+
; GISEL-NEXT: v_readfirstlane_b32 s12, v2
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; GISEL-NEXT: v_readfirstlane_b32 s13, v3
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; GISEL-NEXT: v_readfirstlane_b32 s14, v4
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; GISEL-NEXT: v_readfirstlane_b32 s15, v5
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; GISEL-NEXT: v_readfirstlane_b32 s16, v6
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; GISEL-NEXT: v_readfirstlane_b32 s17, v7
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; GISEL-NEXT: v_readfirstlane_b32 s18, v8
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; GISEL-NEXT: v_readfirstlane_b32 s19, v9
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; GISEL-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[12:13], v[2:3]
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; GISEL-NEXT: v_cmp_eq_u64_e64 s0, s[14:15], v[4:5]
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; GISEL-NEXT: v_cmp_eq_u64_e64 s1, s[16:17], v[6:7]
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; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
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; GISEL-NEXT: v_cmp_eq_u64_e64 s2, s[18:19], v[8:9]
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; GISEL-NEXT: s_and_b32 s0, vcc_lo, s0
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; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_and_b32 s0, s0, s1
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; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_and_b32 s0, s0, s2
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GISEL-NEXT: s_and_saveexec_b32 s0, s0
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; GISEL-NEXT: image_sample_c_lz v1, [v0, v0, v0, v0], s[12:19], s[20:23] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
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; GISEL-NEXT: ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9
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; GISEL-NEXT: ; implicit-def: $vgpr0
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; GISEL-NEXT: s_xor_b32 exec_lo, exec_lo, s0
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; GISEL-NEXT: s_cbranch_execnz .LBB0_1
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; GISEL-NEXT: ; %bb.2:
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; GISEL-NEXT: s_mov_b32 exec_lo, s3
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; GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 1.0
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; GISEL-NEXT: v_mov_b32_e32 v0, 0x7fc00000
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; GISEL-NEXT: s_clause 0x2
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; GISEL-NEXT: image_sample_c_lz v0, [v2, v2, v0, v2], s[4:11], s[20:23] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
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; GISEL-NEXT: image_sample_c_lz v3, [v2, v3, v2, v2], s[4:11], s[20:23] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
133+
; GISEL-NEXT: image_sample_c_lz v4, [v2, v2, v2, v2], s[4:11], s[20:23] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
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; GISEL-NEXT: s_mov_b32 s21, s20
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; GISEL-NEXT: s_waitcnt vmcnt(2)
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; GISEL-NEXT: v_add_f32_e32 v0, v1, v0
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; GISEL-NEXT: s_waitcnt vmcnt(1)
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; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GISEL-NEXT: v_dual_add_f32 v0, v3, v0 :: v_dual_mov_b32 v3, v2
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; GISEL-NEXT: s_waitcnt vmcnt(0)
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; GISEL-NEXT: v_add_f32_e32 v0, v4, v0
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; GISEL-NEXT: v_dual_mov_b32 v4, s20 :: v_dual_mov_b32 v5, s21
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; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GISEL-NEXT: v_mul_f32_e32 v1, 0x3e800000, v0
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; GISEL-NEXT: image_store v[1:3], v[4:5], s[4:11] dim:SQ_RSRC_IMG_2D unorm
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; GISEL-NEXT: s_setpc_b64 s[30:31]
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bb:
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%descriptor = load <8 x i32>, ptr addrspace(1) %arg, align 32
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%needs.waterfall = call float @llvm.amdgcn.image.sample.c.lz.2darray.f32.f32(i32 1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> %descriptor, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
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%i2 = call float @llvm.amdgcn.image.sample.c.lz.2darray.f32.f32(i32 1, float 0.0, float 0.0, float 0x7FF8000000000000, float 0.0, <8 x i32> zeroinitializer, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
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%i3 = fadd float %needs.waterfall, %i2
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%i4 = call float @llvm.amdgcn.image.sample.c.lz.2darray.f32.f32(i32 1, float 0.0, float 1.000000e+00, float 0.0, float 0.0, <8 x i32> zeroinitializer, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
153+
%i5 = fadd float %i4, %i3
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%i6 = call float @llvm.amdgcn.image.sample.c.lz.2darray.f32.f32(i32 1, float 0.0, float 0.0, float 0.0, float 0.0, <8 x i32> zeroinitializer, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
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%i7 = fadd float %i6, %i5
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%i8 = fmul float %i7, 2.500000e-01
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%i9 = insertelement <3 x float> zeroinitializer, float %i8, i64 0
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call void @llvm.amdgcn.image.store.2d.v3f32.i32(<3 x float> %i9, i32 0, i32 0, i32 0, <8 x i32> zeroinitializer, i32 0, i32 0)
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ret void
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}

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