Skip to content

Commit b2accb9

Browse files
lukel97lukel97
authored
[RISCV] Mark V0 regclasses as larger superclasses of non-V0 classes (#70109)
1 parent 14520fa commit b2accb9

16 files changed

+211
-361
lines changed

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -663,6 +663,14 @@ RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
663663
const MachineFunction &) const {
664664
if (RC == &RISCV::VMV0RegClass)
665665
return &RISCV::VRRegClass;
666+
if (RC == &RISCV::VRNoV0RegClass)
667+
return &RISCV::VRRegClass;
668+
if (RC == &RISCV::VRM2NoV0RegClass)
669+
return &RISCV::VRM2RegClass;
670+
if (RC == &RISCV::VRM4NoV0RegClass)
671+
return &RISCV::VRM4RegClass;
672+
if (RC == &RISCV::VRM8NoV0RegClass)
673+
return &RISCV::VRM8RegClass;
666674
return RC;
667675
}
668676

‎llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

Lines changed: 14 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -20,17 +20,13 @@ define void @last_chance_recoloring_failure() {
2020
; CHECK-NEXT: .cfi_offset ra, -8
2121
; CHECK-NEXT: .cfi_offset s0, -16
2222
; CHECK-NEXT: csrr a0, vlenb
23-
; CHECK-NEXT: li a1, 24
24-
; CHECK-NEXT: mul a0, a0, a1
23+
; CHECK-NEXT: slli a0, a0, 4
2524
; CHECK-NEXT: sub sp, sp, a0
26-
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 24 * vlenb
25+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
2726
; CHECK-NEXT: li a0, 55
2827
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
2928
; CHECK-NEXT: vloxseg2ei32.v v16, (a0), v8
30-
; CHECK-NEXT: csrr a0, vlenb
31-
; CHECK-NEXT: slli a0, a0, 3
32-
; CHECK-NEXT: add a0, sp, a0
33-
; CHECK-NEXT: addi a0, a0, 16
29+
; CHECK-NEXT: addi a0, sp, 16
3430
; CHECK-NEXT: csrr a1, vlenb
3531
; CHECK-NEXT: slli a1, a1, 2
3632
; CHECK-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill
@@ -42,47 +38,39 @@ define void @last_chance_recoloring_failure() {
4238
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
4339
; CHECK-NEXT: vfwadd.vv v16, v8, v8, v0.t
4440
; CHECK-NEXT: csrr a0, vlenb
45-
; CHECK-NEXT: slli a0, a0, 4
41+
; CHECK-NEXT: slli a0, a0, 3
4642
; CHECK-NEXT: add a0, sp, a0
4743
; CHECK-NEXT: addi a0, a0, 16
4844
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
4945
; CHECK-NEXT: call func@plt
5046
; CHECK-NEXT: li a0, 32
5147
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
52-
; CHECK-NEXT: vrgather.vv v4, v8, v8, v0.t
48+
; CHECK-NEXT: vrgather.vv v16, v8, v8, v0.t
5349
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
54-
; CHECK-NEXT: csrr a1, vlenb
55-
; CHECK-NEXT: slli a1, a1, 3
56-
; CHECK-NEXT: add a1, sp, a1
57-
; CHECK-NEXT: addi a1, a1, 16
50+
; CHECK-NEXT: addi a1, sp, 16
5851
; CHECK-NEXT: csrr a2, vlenb
5952
; CHECK-NEXT: slli a2, a2, 2
60-
; CHECK-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
53+
; CHECK-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload
6154
; CHECK-NEXT: add a1, a1, a2
62-
; CHECK-NEXT: vl4r.v v28, (a1) # Unknown-size Folded Reload
55+
; CHECK-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
6356
; CHECK-NEXT: csrr a1, vlenb
64-
; CHECK-NEXT: slli a1, a1, 4
57+
; CHECK-NEXT: slli a1, a1, 3
6558
; CHECK-NEXT: add a1, sp, a1
6659
; CHECK-NEXT: addi a1, a1, 16
67-
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
68-
; CHECK-NEXT: vfwsub.wv v8, v16, v24
69-
; CHECK-NEXT: addi a1, sp, 16
70-
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
60+
; CHECK-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
61+
; CHECK-NEXT: vfwsub.wv v8, v0, v20
7162
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
72-
; CHECK-NEXT: vssubu.vv v4, v4, v8, v0.t
63+
; CHECK-NEXT: vssubu.vv v16, v16, v8, v0.t
7364
; CHECK-NEXT: vsetvli zero, s0, e32, m8, tu, mu
7465
; CHECK-NEXT: csrr a0, vlenb
75-
; CHECK-NEXT: slli a0, a0, 4
66+
; CHECK-NEXT: slli a0, a0, 3
7667
; CHECK-NEXT: add a0, sp, a0
7768
; CHECK-NEXT: addi a0, a0, 16
7869
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
79-
; CHECK-NEXT: addi a0, sp, 16
80-
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
8170
; CHECK-NEXT: vfdiv.vv v8, v16, v8, v0.t
8271
; CHECK-NEXT: vse32.v v8, (a0)
8372
; CHECK-NEXT: csrr a0, vlenb
84-
; CHECK-NEXT: li a1, 24
85-
; CHECK-NEXT: mul a0, a0, a1
73+
; CHECK-NEXT: slli a0, a0, 4
8674
; CHECK-NEXT: add sp, sp, a0
8775
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
8876
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload

‎llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -2348,16 +2348,14 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
23482348
; RV32-NEXT: li a3, 40
23492349
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
23502350
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
2351-
; RV32-NEXT: addi a4, sp, 16
2351+
; RV32-NEXT: csrr a4, vlenb
2352+
; RV32-NEXT: slli a4, a4, 4
2353+
; RV32-NEXT: add a4, sp, a4
2354+
; RV32-NEXT: addi a4, a4, 16
23522355
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
23532356
; RV32-NEXT: lui a4, 4080
23542357
; RV32-NEXT: vand.vx v16, v8, a4, v0.t
2355-
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
2356-
; RV32-NEXT: csrr a5, vlenb
2357-
; RV32-NEXT: slli a5, a5, 4
2358-
; RV32-NEXT: add a5, sp, a5
2359-
; RV32-NEXT: addi a5, a5, 16
2360-
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
2358+
; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
23612359
; RV32-NEXT: addi a5, sp, 8
23622360
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
23632361
; RV32-NEXT: vlse64.v v16, (a5), zero
@@ -2369,15 +2367,13 @@ define <vscale x 7 x i64> @vp_bitreverse_nxv7i64(<vscale x 7 x i64> %va, <vscale
23692367
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
23702368
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
23712369
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
2370+
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
23722371
; RV32-NEXT: csrr a5, vlenb
23732372
; RV32-NEXT: slli a5, a5, 4
23742373
; RV32-NEXT: add a5, sp, a5
23752374
; RV32-NEXT: addi a5, a5, 16
23762375
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
23772376
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
2378-
; RV32-NEXT: addi a5, sp, 16
2379-
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
2380-
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
23812377
; RV32-NEXT: csrr a5, vlenb
23822378
; RV32-NEXT: slli a5, a5, 4
23832379
; RV32-NEXT: add a5, sp, a5
@@ -2712,16 +2708,14 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
27122708
; RV32-NEXT: li a3, 40
27132709
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
27142710
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
2715-
; RV32-NEXT: addi a4, sp, 16
2711+
; RV32-NEXT: csrr a4, vlenb
2712+
; RV32-NEXT: slli a4, a4, 4
2713+
; RV32-NEXT: add a4, sp, a4
2714+
; RV32-NEXT: addi a4, a4, 16
27162715
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
27172716
; RV32-NEXT: lui a4, 4080
27182717
; RV32-NEXT: vand.vx v16, v8, a4, v0.t
2719-
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
2720-
; RV32-NEXT: csrr a5, vlenb
2721-
; RV32-NEXT: slli a5, a5, 4
2722-
; RV32-NEXT: add a5, sp, a5
2723-
; RV32-NEXT: addi a5, a5, 16
2724-
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
2718+
; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
27252719
; RV32-NEXT: addi a5, sp, 8
27262720
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
27272721
; RV32-NEXT: vlse64.v v16, (a5), zero
@@ -2733,15 +2727,13 @@ define <vscale x 8 x i64> @vp_bitreverse_nxv8i64(<vscale x 8 x i64> %va, <vscale
27332727
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
27342728
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
27352729
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
2730+
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
27362731
; RV32-NEXT: csrr a5, vlenb
27372732
; RV32-NEXT: slli a5, a5, 4
27382733
; RV32-NEXT: add a5, sp, a5
27392734
; RV32-NEXT: addi a5, a5, 16
27402735
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
27412736
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
2742-
; RV32-NEXT: addi a5, sp, 16
2743-
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
2744-
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
27452737
; RV32-NEXT: csrr a5, vlenb
27462738
; RV32-NEXT: slli a5, a5, 4
27472739
; RV32-NEXT: add a5, sp, a5

‎llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1068,16 +1068,14 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
10681068
; RV32-NEXT: li a3, 40
10691069
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
10701070
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
1071-
; RV32-NEXT: addi a4, sp, 16
1071+
; RV32-NEXT: csrr a4, vlenb
1072+
; RV32-NEXT: slli a4, a4, 4
1073+
; RV32-NEXT: add a4, sp, a4
1074+
; RV32-NEXT: addi a4, a4, 16
10721075
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
10731076
; RV32-NEXT: lui a4, 4080
10741077
; RV32-NEXT: vand.vx v16, v8, a4, v0.t
1075-
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
1076-
; RV32-NEXT: csrr a5, vlenb
1077-
; RV32-NEXT: slli a5, a5, 4
1078-
; RV32-NEXT: add a5, sp, a5
1079-
; RV32-NEXT: addi a5, a5, 16
1080-
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
1078+
; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
10811079
; RV32-NEXT: addi a5, sp, 8
10821080
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
10831081
; RV32-NEXT: vlse64.v v16, (a5), zero
@@ -1089,15 +1087,13 @@ define <vscale x 7 x i64> @vp_bswap_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7
10891087
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
10901088
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
10911089
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
1090+
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
10921091
; RV32-NEXT: csrr a0, vlenb
10931092
; RV32-NEXT: slli a0, a0, 4
10941093
; RV32-NEXT: add a0, sp, a0
10951094
; RV32-NEXT: addi a0, a0, 16
10961095
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
10971096
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
1098-
; RV32-NEXT: addi a0, sp, 16
1099-
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
1100-
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
11011097
; RV32-NEXT: csrr a0, vlenb
11021098
; RV32-NEXT: slli a0, a0, 4
11031099
; RV32-NEXT: add a0, sp, a0
@@ -1317,16 +1313,14 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
13171313
; RV32-NEXT: li a3, 40
13181314
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
13191315
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
1320-
; RV32-NEXT: addi a4, sp, 16
1316+
; RV32-NEXT: csrr a4, vlenb
1317+
; RV32-NEXT: slli a4, a4, 4
1318+
; RV32-NEXT: add a4, sp, a4
1319+
; RV32-NEXT: addi a4, a4, 16
13211320
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
13221321
; RV32-NEXT: lui a4, 4080
13231322
; RV32-NEXT: vand.vx v16, v8, a4, v0.t
1324-
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
1325-
; RV32-NEXT: csrr a5, vlenb
1326-
; RV32-NEXT: slli a5, a5, 4
1327-
; RV32-NEXT: add a5, sp, a5
1328-
; RV32-NEXT: addi a5, a5, 16
1329-
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
1323+
; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
13301324
; RV32-NEXT: addi a5, sp, 8
13311325
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
13321326
; RV32-NEXT: vlse64.v v16, (a5), zero
@@ -1338,15 +1332,13 @@ define <vscale x 8 x i64> @vp_bswap_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8
13381332
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
13391333
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
13401334
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
1335+
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
13411336
; RV32-NEXT: csrr a0, vlenb
13421337
; RV32-NEXT: slli a0, a0, 4
13431338
; RV32-NEXT: add a0, sp, a0
13441339
; RV32-NEXT: addi a0, a0, 16
13451340
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
13461341
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
1347-
; RV32-NEXT: addi a0, sp, 16
1348-
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
1349-
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
13501342
; RV32-NEXT: csrr a0, vlenb
13511343
; RV32-NEXT: slli a0, a0, 4
13521344
; RV32-NEXT: add a0, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2070,7 +2070,8 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
20702070
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb
20712071
; RV32-NEXT: vmv1r.v v24, v0
20722072
; RV32-NEXT: csrr a1, vlenb
2073-
; RV32-NEXT: slli a1, a1, 5
2073+
; RV32-NEXT: li a2, 40
2074+
; RV32-NEXT: mul a1, a1, a2
20742075
; RV32-NEXT: add a1, sp, a1
20752076
; RV32-NEXT: addi a1, a1, 16
20762077
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
@@ -2089,35 +2090,30 @@ define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x
20892090
; RV32-NEXT: addi a3, a3, -1
20902091
; RV32-NEXT: and a2, a3, a2
20912092
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
2092-
; RV32-NEXT: vsrl.vi v8, v16, 1, v0.t
20932093
; RV32-NEXT: csrr a3, vlenb
20942094
; RV32-NEXT: li a4, 40
20952095
; RV32-NEXT: mul a3, a3, a4
20962096
; RV32-NEXT: add a3, sp, a3
20972097
; RV32-NEXT: addi a3, a3, 16
2098-
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
2098+
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
2099+
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
20992100
; RV32-NEXT: lui a3, 349525
21002101
; RV32-NEXT: addi a3, a3, 1365
21012102
; RV32-NEXT: vsetvli a4, zero, e32, m8, ta, ma
2102-
; RV32-NEXT: vmv.v.x v16, a3
2103+
; RV32-NEXT: vmv.v.x v8, a3
21032104
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
21042105
; RV32-NEXT: csrr a3, vlenb
21052106
; RV32-NEXT: li a4, 24
21062107
; RV32-NEXT: mul a3, a3, a4
21072108
; RV32-NEXT: add a3, sp, a3
21082109
; RV32-NEXT: addi a3, a3, 16
2109-
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
2110+
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
2111+
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
21102112
; RV32-NEXT: csrr a3, vlenb
21112113
; RV32-NEXT: li a4, 40
21122114
; RV32-NEXT: mul a3, a3, a4
21132115
; RV32-NEXT: add a3, sp, a3
21142116
; RV32-NEXT: addi a3, a3, 16
2115-
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
2116-
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
2117-
; RV32-NEXT: csrr a3, vlenb
2118-
; RV32-NEXT: slli a3, a3, 5
2119-
; RV32-NEXT: add a3, sp, a3
2120-
; RV32-NEXT: addi a3, a3, 16
21212117
; RV32-NEXT: vl8r.v v16, (a3) # Unknown-size Folded Reload
21222118
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
21232119
; RV32-NEXT: csrr a3, vlenb

‎llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2439,13 +2439,13 @@ define <vscale x 16 x i64> @vp_cttz_nxv16i64(<vscale x 16 x i64> %va, <vscale x
24392439
; RV32-NEXT: add a0, sp, a0
24402440
; RV32-NEXT: addi a0, a0, 16
24412441
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
2442-
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
2442+
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
24432443
; RV32-NEXT: csrr a0, vlenb
24442444
; RV32-NEXT: li a1, 40
24452445
; RV32-NEXT: mul a0, a0, a1
24462446
; RV32-NEXT: add a0, sp, a0
24472447
; RV32-NEXT: addi a0, a0, 16
2448-
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
2448+
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
24492449
; RV32-NEXT: csrr a0, vlenb
24502450
; RV32-NEXT: li a1, 24
24512451
; RV32-NEXT: mul a0, a0, a1

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1710,16 +1710,14 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
17101710
; RV32-NEXT: li a3, 40
17111711
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
17121712
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
1713-
; RV32-NEXT: addi a4, sp, 48
1713+
; RV32-NEXT: csrr a4, vlenb
1714+
; RV32-NEXT: slli a4, a4, 4
1715+
; RV32-NEXT: add a4, sp, a4
1716+
; RV32-NEXT: addi a4, a4, 48
17141717
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
17151718
; RV32-NEXT: lui a4, 4080
17161719
; RV32-NEXT: vand.vx v16, v8, a4, v0.t
1717-
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
1718-
; RV32-NEXT: csrr a5, vlenb
1719-
; RV32-NEXT: slli a5, a5, 4
1720-
; RV32-NEXT: add a5, sp, a5
1721-
; RV32-NEXT: addi a5, a5, 48
1722-
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
1720+
; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
17231721
; RV32-NEXT: addi a5, sp, 16
17241722
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
17251723
; RV32-NEXT: vlse64.v v16, (a5), zero
@@ -1731,15 +1729,13 @@ define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroex
17311729
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
17321730
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
17331731
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
1732+
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
17341733
; RV32-NEXT: csrr a5, vlenb
17351734
; RV32-NEXT: slli a5, a5, 4
17361735
; RV32-NEXT: add a5, sp, a5
17371736
; RV32-NEXT: addi a5, a5, 48
17381737
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
17391738
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
1740-
; RV32-NEXT: addi a5, sp, 48
1741-
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
1742-
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
17431739
; RV32-NEXT: csrr a5, vlenb
17441740
; RV32-NEXT: slli a5, a5, 4
17451741
; RV32-NEXT: add a5, sp, a5
@@ -2080,16 +2076,14 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
20802076
; RV32-NEXT: li a3, 40
20812077
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
20822078
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
2083-
; RV32-NEXT: addi a4, sp, 48
2079+
; RV32-NEXT: csrr a4, vlenb
2080+
; RV32-NEXT: slli a4, a4, 4
2081+
; RV32-NEXT: add a4, sp, a4
2082+
; RV32-NEXT: addi a4, a4, 48
20842083
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
20852084
; RV32-NEXT: lui a4, 4080
20862085
; RV32-NEXT: vand.vx v16, v8, a4, v0.t
2087-
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
2088-
; RV32-NEXT: csrr a5, vlenb
2089-
; RV32-NEXT: slli a5, a5, 4
2090-
; RV32-NEXT: add a5, sp, a5
2091-
; RV32-NEXT: addi a5, a5, 48
2092-
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
2086+
; RV32-NEXT: vsll.vi v24, v16, 24, v0.t
20932087
; RV32-NEXT: addi a5, sp, 16
20942088
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
20952089
; RV32-NEXT: vlse64.v v16, (a5), zero
@@ -2101,15 +2095,13 @@ define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroex
21012095
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
21022096
; RV32-NEXT: vand.vv v16, v8, v16, v0.t
21032097
; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
2098+
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
21042099
; RV32-NEXT: csrr a5, vlenb
21052100
; RV32-NEXT: slli a5, a5, 4
21062101
; RV32-NEXT: add a5, sp, a5
21072102
; RV32-NEXT: addi a5, a5, 48
21082103
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
21092104
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
2110-
; RV32-NEXT: addi a5, sp, 48
2111-
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
2112-
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
21132105
; RV32-NEXT: csrr a5, vlenb
21142106
; RV32-NEXT: slli a5, a5, 4
21152107
; RV32-NEXT: add a5, sp, a5

0 commit comments

Comments
 (0)