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Revert "[ARM] R11 not pushed adjacent to link register with PAC-M and… (#84019)
… AAPCS frame chain fix (#82801)" This reverts commit 00e4a41. This patch was found to cause miscompilations and compilation failures.
1 parent a1a590e commit b2c16e7

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6 files changed

+93
-297
lines changed

6 files changed

+93
-297
lines changed

‎llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -62,16 +62,14 @@ ARMBaseRegisterInfo::ARMBaseRegisterInfo()
6262
const MCPhysReg*
6363
ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
6464
const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
65-
bool UseSplitPush = (STI.getPushPopSplitVariation(*MF) ==
66-
ARMSubtarget::PushPopSplitVariation::R7Split);
65+
bool UseSplitPush = STI.splitFramePushPop(*MF);
6766
const Function &F = MF->getFunction();
6867

6968
if (F.getCallingConv() == CallingConv::GHC) {
7069
// GHC set of callee saved regs is empty as all those regs are
7170
// used for passing STG regs around
7271
return CSR_NoRegs_SaveList;
73-
} else if (STI.getPushPopSplitVariation(*MF) ==
74-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
72+
} else if (STI.splitFramePointerPush(*MF)) {
7573
return CSR_Win_SplitFP_SaveList;
7674
} else if (F.getCallingConv() == CallingConv::CFGuard_Check) {
7775
return CSR_Win_AAPCS_CFGuard_Check_SaveList;

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp

Lines changed: 60 additions & 155 deletions
Original file line numberDiff line numberDiff line change
@@ -718,14 +718,9 @@ static int getMaxFPOffset(const ARMSubtarget &STI, const ARMFunctionInfo &AFI,
718718
// This is a conservative estimation: Assume the frame pointer being r7 and
719719
// pc("r15") up to r8 getting spilled before (= 8 registers).
720720
int MaxRegBytes = 8 * 4;
721-
if (STI.getPushPopSplitVariation(MF) ==
722-
ARMSubtarget::PushPopSplitVariation::R11SplitAAPCSBranchSigning)
721+
if (STI.splitFramePointerPush(MF)) {
723722
// Here, r11 can be stored below all of r4-r15 (3 registers more than
724-
// above).
725-
MaxRegBytes = 11 * 4;
726-
if (STI.getPushPopSplitVariation(MF) ==
727-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
728-
// Here, r11 can be stored below all of r4-r15 plus d8-d15.
723+
// above), plus d8-d15.
729724
MaxRegBytes = 11 * 4 + 8 * 8;
730725
}
731726
int FPCXTSaveSize =
@@ -793,10 +788,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
793788
}
794789

795790
// Determine spill area sizes.
796-
if (STI.getPushPopSplitVariation(MF) ==
797-
ARMSubtarget::PushPopSplitVariation::R11SplitAAPCSBranchSigning ||
798-
STI.getPushPopSplitVariation(MF) ==
799-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
791+
if (STI.splitFramePointerPush(MF)) {
800792
for (const CalleeSavedInfo &I : CSI) {
801793
Register Reg = I.getReg();
802794
int FI = I.getFrameIdx();
@@ -842,8 +834,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
842834
case ARM::R10:
843835
case ARM::R11:
844836
case ARM::R12:
845-
if (STI.getPushPopSplitVariation(MF) ==
846-
ARMSubtarget::PushPopSplitVariation::R7Split) {
837+
if (STI.splitFramePushPop(MF)) {
847838
GPRCS2Size += 4;
848839
break;
849840
}
@@ -906,15 +897,13 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
906897
unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
907898
Align DPRAlign = DPRCSSize ? std::min(Align(8), Alignment) : Align(4);
908899
unsigned DPRGapSize = GPRCS1Size + FPCXTSaveSize + ArgRegsSaveSize;
909-
if (STI.getPushPopSplitVariation(MF) !=
910-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
900+
if (!STI.splitFramePointerPush(MF)) {
911901
DPRGapSize += GPRCS2Size;
912902
}
913903
DPRGapSize %= DPRAlign.value();
914904

915905
unsigned DPRCSOffset;
916-
if (STI.getPushPopSplitVariation(MF) ==
917-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
906+
if (STI.splitFramePointerPush(MF)) {
918907
DPRCSOffset = GPRCS1Offset - DPRGapSize - DPRCSSize;
919908
GPRCS2Offset = DPRCSOffset - GPRCS2Size;
920909
} else {
@@ -933,10 +922,8 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
933922
AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
934923
AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
935924

936-
// Move past area 2, unless following the CSR_Win_SplitFP calling convention.
937-
if (GPRCS2Size > 0 &&
938-
STI.getPushPopSplitVariation(MF) !=
939-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
925+
// Move past area 2.
926+
if (GPRCS2Size > 0 && !STI.splitFramePointerPush(MF)) {
940927
GPRCS2Push = LastPush = MBBI++;
941928
DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
942929
}
@@ -976,18 +963,13 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
976963
} else
977964
NumBytes = DPRCSOffset;
978965

979-
// Move past area 2 if following the CSR_Win_SplitFP calling convention.
980-
if (GPRCS2Size > 0 &&
981-
STI.getPushPopSplitVariation(MF) ==
982-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
966+
if (GPRCS2Size > 0 && STI.splitFramePointerPush(MF)) {
983967
GPRCS2Push = LastPush = MBBI++;
984968
DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
985969
}
986970

987971
bool NeedsWinCFIStackAlloc = NeedsWinCFI;
988-
if (STI.getPushPopSplitVariation(MF) ==
989-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind &&
990-
HasFP)
972+
if (STI.splitFramePointerPush(MF) && HasFP)
991973
NeedsWinCFIStackAlloc = false;
992974

993975
if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
@@ -1092,10 +1074,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
10921074
AfterPush = std::next(GPRCS1Push);
10931075
unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push);
10941076
int FPOffset = PushSize + FramePtrOffsetInPush;
1095-
if (STI.getPushPopSplitVariation(MF) ==
1096-
ARMSubtarget::PushPopSplitVariation::R11SplitAAPCSBranchSigning ||
1097-
STI.getPushPopSplitVariation(MF) ==
1098-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
1077+
if (STI.splitFramePointerPush(MF)) {
10991078
AfterPush = std::next(GPRCS2Push);
11001079
emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII,
11011080
FramePtr, ARM::SP, 0, MachineInstr::FrameSetup);
@@ -1127,9 +1106,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
11271106
// instructions below don't need to be replayed to unwind the stack.
11281107
if (NeedsWinCFI && MBBI != MBB.begin()) {
11291108
MachineBasicBlock::iterator End = MBBI;
1130-
if (HasFP &&
1131-
STI.getPushPopSplitVariation(MF) ==
1132-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind)
1109+
if (HasFP && STI.splitFramePointerPush(MF))
11331110
End = AfterPush;
11341111
insertSEHRange(MBB, {}, End, TII, MachineInstr::FrameSetup);
11351112
BuildMI(MBB, End, dl, TII.get(ARM::SEH_PrologEnd))
@@ -1141,103 +1118,51 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
11411118
// the necessary DWARF cf instructions to describe the situation. Start by
11421119
// recording where each register ended up:
11431120
if (GPRCS1Size > 0 && !NeedsWinCFI) {
1144-
if (STI.getPushPopSplitVariation(MF) ==
1145-
ARMSubtarget::PushPopSplitVariation::R11SplitAAPCSBranchSigning) {
1146-
MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
1147-
int CFIIndex;
1148-
for (const auto &Entry : CSI) {
1149-
Register Reg = Entry.getReg();
1150-
int FI = Entry.getFrameIdx();
1151-
switch (Reg) {
1152-
case ARM::R0:
1153-
case ARM::R1:
1154-
case ARM::R2:
1155-
case ARM::R3:
1156-
case ARM::R4:
1157-
case ARM::R5:
1158-
case ARM::R6:
1159-
case ARM::R7:
1160-
case ARM::R8:
1161-
case ARM::R9:
1162-
case ARM::R10:
1163-
case ARM::R12:
1164-
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1165-
nullptr, MRI->getDwarfRegNum(Reg, true),
1166-
MFI.getObjectOffset(FI)));
1167-
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1168-
.addCFIIndex(CFIIndex)
1169-
.setMIFlags(MachineInstr::FrameSetup);
1170-
break;
1171-
}
1172-
}
1173-
} else {
1174-
MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
1175-
int CFIIndex;
1176-
for (const auto &Entry : CSI) {
1177-
Register Reg = Entry.getReg();
1178-
int FI = Entry.getFrameIdx();
1179-
switch (Reg) {
1180-
case ARM::R8:
1181-
case ARM::R9:
1182-
case ARM::R10:
1183-
case ARM::R11:
1184-
case ARM::R12:
1185-
if (STI.getPushPopSplitVariation(MF) ==
1186-
ARMSubtarget::PushPopSplitVariation::R7Split)
1187-
break;
1188-
[[fallthrough]];
1189-
case ARM::R0:
1190-
case ARM::R1:
1191-
case ARM::R2:
1192-
case ARM::R3:
1193-
case ARM::R4:
1194-
case ARM::R5:
1195-
case ARM::R6:
1196-
case ARM::R7:
1197-
case ARM::LR:
1198-
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1199-
nullptr, MRI->getDwarfRegNum(Reg, true),
1200-
MFI.getObjectOffset(FI)));
1201-
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1202-
.addCFIIndex(CFIIndex)
1203-
.setMIFlags(MachineInstr::FrameSetup);
1121+
MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
1122+
int CFIIndex;
1123+
for (const auto &Entry : CSI) {
1124+
Register Reg = Entry.getReg();
1125+
int FI = Entry.getFrameIdx();
1126+
switch (Reg) {
1127+
case ARM::R8:
1128+
case ARM::R9:
1129+
case ARM::R10:
1130+
case ARM::R11:
1131+
case ARM::R12:
1132+
if (STI.splitFramePushPop(MF))
12041133
break;
1205-
}
1134+
[[fallthrough]];
1135+
case ARM::R0:
1136+
case ARM::R1:
1137+
case ARM::R2:
1138+
case ARM::R3:
1139+
case ARM::R4:
1140+
case ARM::R5:
1141+
case ARM::R6:
1142+
case ARM::R7:
1143+
case ARM::LR:
1144+
CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
1145+
nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
1146+
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1147+
.addCFIIndex(CFIIndex)
1148+
.setMIFlags(MachineInstr::FrameSetup);
1149+
break;
12061150
}
12071151
}
12081152
}
12091153

12101154
if (GPRCS2Size > 0 && !NeedsWinCFI) {
12111155
MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
1212-
if (STI.getPushPopSplitVariation(MF) ==
1213-
ARMSubtarget::PushPopSplitVariation::R11SplitAAPCSBranchSigning) {
1214-
for (const auto &Entry : CSI) {
1215-
Register Reg = Entry.getReg();
1216-
int FI = Entry.getFrameIdx();
1217-
switch (Reg) {
1218-
case ARM::R11:
1219-
case ARM::LR:
1220-
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
1221-
unsigned Offset = MFI.getObjectOffset(FI);
1222-
unsigned CFIIndex = MF.addFrameInst(
1223-
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
1224-
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1225-
.addCFIIndex(CFIIndex)
1226-
.setMIFlags(MachineInstr::FrameSetup);
1227-
break;
1228-
}
1229-
}
1230-
} else {
1231-
MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
1232-
for (const auto &Entry : CSI) {
1233-
Register Reg = Entry.getReg();
1234-
int FI = Entry.getFrameIdx();
1235-
switch (Reg) {
1236-
case ARM::R8:
1237-
case ARM::R9:
1238-
case ARM::R10:
1239-
case ARM::R11:
1240-
case ARM::R12:
1156+
for (const auto &Entry : CSI) {
1157+
Register Reg = Entry.getReg();
1158+
int FI = Entry.getFrameIdx();
1159+
switch (Reg) {
1160+
case ARM::R8:
1161+
case ARM::R9:
1162+
case ARM::R10:
1163+
case ARM::R11:
1164+
case ARM::R12:
1165+
if (STI.splitFramePushPop(MF)) {
12411166
unsigned DwarfReg = MRI->getDwarfRegNum(
12421167
Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true);
12431168
unsigned Offset = MFI.getObjectOffset(FI);
@@ -1246,8 +1171,8 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
12461171
BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
12471172
.addCFIIndex(CFIIndex)
12481173
.setMIFlags(MachineInstr::FrameSetup);
1249-
break;
12501174
}
1175+
break;
12511176
}
12521177
}
12531178
}
@@ -1457,9 +1382,7 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
14571382
MachineInstr::FrameDestroy);
14581383

14591384
// Increment past our save areas.
1460-
if (AFI->getGPRCalleeSavedArea2Size() &&
1461-
STI.getPushPopSplitVariation(MF) ==
1462-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind)
1385+
if (AFI->getGPRCalleeSavedArea2Size() && STI.splitFramePointerPush(MF))
14631386
MBBI++;
14641387

14651388
if (MBBI != MBB.end() && AFI->getDPRCalleeSavedAreaSize()) {
@@ -1476,9 +1399,7 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF,
14761399
MachineInstr::FrameDestroy);
14771400
}
14781401

1479-
if (AFI->getGPRCalleeSavedArea2Size() &&
1480-
STI.getPushPopSplitVariation(MF) !=
1481-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind)
1402+
if (AFI->getGPRCalleeSavedArea2Size() && !STI.splitFramePointerPush(MF))
14821403
MBBI++;
14831404
if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
14841405

@@ -1618,9 +1539,7 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
16181539
unsigned LastReg = 0;
16191540
for (; i != 0; --i) {
16201541
Register Reg = CSI[i-1].getReg();
1621-
if (!(Func)(Reg, STI.getPushPopSplitVariation(MF) ==
1622-
ARMSubtarget::PushPopSplitVariation::R7Split))
1623-
continue;
1542+
if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
16241543

16251544
// D-registers in the aligned area DPRCS2 are NOT spilled here.
16261545
if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
@@ -1713,21 +1632,15 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
17131632
for (; i != 0; --i) {
17141633
CalleeSavedInfo &Info = CSI[i-1];
17151634
Register Reg = Info.getReg();
1716-
if (!(Func)(Reg, STI.getPushPopSplitVariation(MF) ==
1717-
ARMSubtarget::PushPopSplitVariation::R7Split))
1718-
continue;
1635+
if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
17191636

17201637
// The aligned reloads from area DPRCS2 are not inserted here.
17211638
if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
17221639
continue;
17231640
if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
17241641
!isCmseEntry && !isTrap && AFI->getArgumentStackToRestore() == 0 &&
17251642
STI.hasV5TOps() && MBB.succ_empty() && !hasPAC &&
1726-
(STI.getPushPopSplitVariation(MF) !=
1727-
ARMSubtarget::PushPopSplitVariation::
1728-
R11SplitAAPCSBranchSigning &&
1729-
STI.getPushPopSplitVariation(MF) !=
1730-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind)) {
1643+
!STI.splitFramePointerPush(MF)) {
17311644
Reg = ARM::PC;
17321645
// Fold the return instruction into the LDM.
17331646
DeleteRet = true;
@@ -2088,10 +2001,7 @@ bool ARMFrameLowering::spillCalleeSavedRegisters(
20882001
.addImm(-4)
20892002
.add(predOps(ARMCC::AL));
20902003
}
2091-
if (STI.getPushPopSplitVariation(MF) ==
2092-
ARMSubtarget::PushPopSplitVariation::R11SplitAAPCSBranchSigning ||
2093-
STI.getPushPopSplitVariation(MF) ==
2094-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
2004+
if (STI.splitFramePointerPush(MF)) {
20952005
emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false,
20962006
&isSplitFPArea1Register, 0, MachineInstr::FrameSetup);
20972007
emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
@@ -2136,10 +2046,7 @@ bool ARMFrameLowering::restoreCalleeSavedRegisters(
21362046
unsigned LdrOpc =
21372047
AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
21382048
unsigned FltOpc = ARM::VLDMDIA_UPD;
2139-
if (STI.getPushPopSplitVariation(MF) ==
2140-
ARMSubtarget::PushPopSplitVariation::R11SplitAAPCSBranchSigning ||
2141-
STI.getPushPopSplitVariation(MF) ==
2142-
ARMSubtarget::PushPopSplitVariation::R11SplitWindowsSEHUnwind) {
2049+
if (STI.splitFramePointerPush(MF)) {
21432050
emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
21442051
&isSplitFPArea2Register, 0);
21452052
emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
@@ -2455,8 +2362,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
24552362
if (Spilled) {
24562363
NumGPRSpills++;
24572364

2458-
if (STI.getPushPopSplitVariation(MF) !=
2459-
ARMSubtarget::PushPopSplitVariation::R7Split) {
2365+
if (!STI.splitFramePushPop(MF)) {
24602366
if (Reg == ARM::LR)
24612367
LRSpilled = true;
24622368
CS1Spilled = true;
@@ -2478,8 +2384,7 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
24782384
break;
24792385
}
24802386
} else {
2481-
if (STI.getPushPopSplitVariation(MF) !=
2482-
ARMSubtarget::PushPopSplitVariation::R7Split) {
2387+
if (!STI.splitFramePushPop(MF)) {
24832388
UnspilledCS1GPRs.push_back(Reg);
24842389
continue;
24852390
}

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