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[RISCV] Move getSmallestVTForIndex so it can be used by lowerINSERT_VECTOR_ELT. NFC
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -7345,6 +7345,32 @@ RISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
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return Result;
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}
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7348+
// Given a scalable vector type and an index into it, returns the type for the
7349+
// smallest subvector that the index fits in. This can be used to reduce LMUL
7350+
// for operations like vslidedown.
7351+
//
7352+
// E.g. With Zvl128b, index 3 in a nxv4i32 fits within the first nxv2i32.
7353+
static std::optional<MVT>
7354+
getSmallestVTForIndex(MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG &DAG,
7355+
const RISCVSubtarget &Subtarget) {
7356+
assert(VecVT.isScalableVector());
7357+
const unsigned EltSize = VecVT.getScalarSizeInBits();
7358+
const unsigned VectorBitsMin = Subtarget.getRealMinVLen();
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const unsigned MinVLMAX = VectorBitsMin / EltSize;
7360+
MVT SmallerVT;
7361+
if (MaxIdx < MinVLMAX)
7362+
SmallerVT = getLMUL1VT(VecVT);
7363+
else if (MaxIdx < MinVLMAX * 2)
7364+
SmallerVT = getLMUL1VT(VecVT).getDoubleNumVectorElementsVT();
7365+
else if (MaxIdx < MinVLMAX * 4)
7366+
SmallerVT = getLMUL1VT(VecVT)
7367+
.getDoubleNumVectorElementsVT()
7368+
.getDoubleNumVectorElementsVT();
7369+
if (!SmallerVT.isValid() || !VecVT.bitsGT(SmallerVT))
7370+
return std::nullopt;
7371+
return SmallerVT;
7372+
}
7373+
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// Custom-legalize INSERT_VECTOR_ELT so that the value is inserted into the
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// first position of a vector, and that vector is slid up to the insert index.
73507376
// By limiting the active vector length to index+1 and merging with the
@@ -7466,32 +7492,6 @@ SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
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return convertFromScalableVector(VecVT, Slideup, DAG, Subtarget);
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}
74687494

7469-
// Given a scalable vector type and an index into it, returns the type for the
7470-
// smallest subvector that the index fits in. This can be used to reduce LMUL
7471-
// for operations like vslidedown.
7472-
//
7473-
// E.g. With Zvl128b, index 3 in a nxv4i32 fits within the first nxv2i32.
7474-
static std::optional<MVT>
7475-
getSmallestVTForIndex(MVT VecVT, unsigned MaxIdx, SDLoc DL, SelectionDAG &DAG,
7476-
const RISCVSubtarget &Subtarget) {
7477-
assert(VecVT.isScalableVector());
7478-
const unsigned EltSize = VecVT.getScalarSizeInBits();
7479-
const unsigned VectorBitsMin = Subtarget.getRealMinVLen();
7480-
const unsigned MinVLMAX = VectorBitsMin / EltSize;
7481-
MVT SmallerVT;
7482-
if (MaxIdx < MinVLMAX)
7483-
SmallerVT = getLMUL1VT(VecVT);
7484-
else if (MaxIdx < MinVLMAX * 2)
7485-
SmallerVT = getLMUL1VT(VecVT).getDoubleNumVectorElementsVT();
7486-
else if (MaxIdx < MinVLMAX * 4)
7487-
SmallerVT = getLMUL1VT(VecVT)
7488-
.getDoubleNumVectorElementsVT()
7489-
.getDoubleNumVectorElementsVT();
7490-
if (!SmallerVT.isValid() || !VecVT.bitsGT(SmallerVT))
7491-
return std::nullopt;
7492-
return SmallerVT;
7493-
}
7494-
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// Custom-lower EXTRACT_VECTOR_ELT operations to slide the vector down, then
74967496
// extract the first element: (extractelt (slidedown vec, idx), 0). For integer
74977497
// types this is done using VMV_X_S to allow us to glean information about the

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