Combined the fp4 and fp8 queries in getFPDstSelType.

Author: pravinjagtap

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

@@ -920,22 +920,23 @@ getDstSelForwardingOperand(const MachineInstr &MI, const GCNSubtarget &ST) {
         return TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
   }
 
+  AMDGPU::FPType IsFP4OrFP8ConvOpc = AMDGPU::getFPDstSelType(Opcode);
   if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::op_sel)) {
     // Type 2: VOP3 which write the hi bits
     if (TII->getNamedImmOperand(MI, AMDGPU::OpName::src0_modifiers) &
         SISrcMods::DST_OP_SEL)
       return TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
 
     // Type 3: FP8DstSelInst with op_sel[3:2] != 0)
-    if (AMDGPU::isFP8DstSelInst(Opcode) &&
+    if (IsFP4OrFP8ConvOpc == AMDGPU::FPType::FP8 &&
         (TII->getNamedImmOperand(MI, AMDGPU::OpName::src2_modifiers) &
          SISrcMods::OP_SEL_0))
       return TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
   }
 
   // Special case: nop is required for all the opsel values for fp4 sr variant
   // cvt scale instructions
-  if (AMDGPU::isFP4DstSelInst(Opcode))
+  if (IsFP4OrFP8ConvOpc == AMDGPU::FPType::FP4)
     return TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
 
   return nullptr;

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

@@ -664,14 +664,16 @@ bool isTrue16Inst(unsigned Opc) {
   return Info ? Info->IsTrue16 : false;
 }
 
-bool isFP8DstSelInst(unsigned Opc) {
-  const FP8DstByteSelInfo *Info = getFP8DstByteSelHelper(Opc);
-  return Info ? Info->HasFP8DstByteSel : false;
-}
+FPType getFPDstSelType(unsigned Opc) {
+  const FP8DstByteSelInfo *Info8 = getFP8DstByteSelHelper(Opc);
+  if (Info8 && Info8->HasFP8DstByteSel)
+    return FPType::FP8;
+
+  const FP4DstByteSelInfo *Info4 = getFP4DstByteSelHelper(Opc);
+  if (Info4 && Info4->HasFP4DstByteSel)
+    return FPType::FP4;
 
-bool isFP4DstSelInst(unsigned Opc) {
-  const FP4DstByteSelInfo *Info = getFP4DstByteSelHelper(Opc);
-  return Info ? Info->HasFP4DstByteSel : false;
+  return FPType::None;
 }
 
 unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc) {

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

@@ -55,6 +55,8 @@ static constexpr unsigned GFX12 = 1;
 
 enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5, AMDHSA_COV6 = 6 };
 
+enum class FPType { None, FP4, FP8 };
+
 /// \returns True if \p STI is AMDHSA.
 bool isHsaAbi(const MCSubtargetInfo &STI);
 
@@ -885,10 +887,7 @@ LLVM_READONLY
 bool isTrue16Inst(unsigned Opc);
 
 LLVM_READONLY
-bool isFP8DstSelInst(unsigned Opc);
-
-LLVM_READONLY
-bool isFP4DstSelInst(unsigned Opc);
+FPType getFPDstSelType(unsigned Opc);
 
 LLVM_READONLY
 bool isInvalidSingleUseConsumerInst(unsigned Opc);