Skip to content

Commit b356a30

Browse files
MaskRayMaskRay
committed
[Mips] Format some MCTargetDesc files. NFC
In preparation for #127581
1 parent bc35510 commit b356a30

File tree

3 files changed

+278
-275
lines changed

3 files changed

+278
-275
lines changed

‎llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

Lines changed: 14 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -351,10 +351,11 @@ std::optional<MCFixupKind> MipsAsmBackend::getFixupKind(StringRef Name) const {
351351
const MCFixupKindInfo &MipsAsmBackend::
352352
getFixupKindInfo(MCFixupKind Kind) const {
353353
const static MCFixupKindInfo LittleEndianInfos[] = {
354-
// This table *must* be in same the order of fixup_* kinds in
355-
// MipsFixupKinds.h.
356-
//
357-
// name offset bits flags
354+
// This table *must* be in same the order of fixup_* kinds in
355+
// MipsFixupKinds.h.
356+
//
357+
// name offset bits flags
358+
// clang-format off
358359
{ "fixup_Mips_16", 0, 16, 0 },
359360
{ "fixup_Mips_32", 0, 32, 0 },
360361
{ "fixup_Mips_REL32", 0, 32, 0 },
@@ -424,16 +425,18 @@ getFixupKindInfo(MCFixupKind Kind) const {
424425
{ "fixup_Mips_SUB", 0, 64, 0 },
425426
{ "fixup_MICROMIPS_SUB", 0, 64, 0 },
426427
{ "fixup_Mips_JALR", 0, 32, 0 },
427-
{ "fixup_MICROMIPS_JALR", 0, 32, 0 }
428+
{ "fixup_MICROMIPS_JALR", 0, 32, 0 },
429+
// clang-format on
428430
};
429431
static_assert(std::size(LittleEndianInfos) == Mips::NumTargetFixupKinds,
430432
"Not all MIPS little endian fixup kinds added!");
431433

432434
const static MCFixupKindInfo BigEndianInfos[] = {
433-
// This table *must* be in same the order of fixup_* kinds in
434-
// MipsFixupKinds.h.
435-
//
436-
// name offset bits flags
435+
// This table *must* be in same the order of fixup_* kinds in
436+
// MipsFixupKinds.h.
437+
//
438+
// name offset bits flags
439+
// clang-format off
437440
{ "fixup_Mips_16", 16, 16, 0 },
438441
{ "fixup_Mips_32", 0, 32, 0 },
439442
{ "fixup_Mips_REL32", 0, 32, 0 },
@@ -503,7 +506,8 @@ getFixupKindInfo(MCFixupKind Kind) const {
503506
{ "fixup_Mips_SUB", 0, 64, 0 },
504507
{ "fixup_MICROMIPS_SUB", 0, 64, 0 },
505508
{ "fixup_Mips_JALR", 0, 32, 0 },
506-
{ "fixup_MICROMIPS_JALR", 0, 32, 0 }
509+
{ "fixup_MICROMIPS_JALR", 0, 32, 0 },
510+
// clang-format on
507511
};
508512
static_assert(std::size(BigEndianInfos) == Mips::NumTargetFixupKinds,
509513
"Not all MIPS big endian fixup kinds added!");

‎llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h

Lines changed: 115 additions & 115 deletions
Original file line numberDiff line numberDiff line change
@@ -26,120 +26,120 @@ namespace llvm {
2626
/// instruction info tracks.
2727
///
2828
namespace MipsII {
29-
/// Target Operand Flag enum.
30-
enum TOF {
31-
//===------------------------------------------------------------------===//
32-
// Mips Specific MachineOperand flags.
33-
34-
MO_NO_FLAG,
35-
36-
/// MO_GOT - Represents the offset into the global offset table at which
37-
/// the address the relocation entry symbol resides during execution.
38-
MO_GOT,
39-
40-
/// MO_GOT_CALL - Represents the offset into the global offset table at
41-
/// which the address of a call site relocation entry symbol resides
42-
/// during execution. This is different from the above since this flag
43-
/// can only be present in call instructions.
44-
MO_GOT_CALL,
45-
46-
/// MO_GPREL - Represents the offset from the current gp value to be used
47-
/// for the relocatable object file being produced.
48-
MO_GPREL,
49-
50-
/// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol
51-
/// address.
52-
MO_ABS_HI,
53-
MO_ABS_LO,
54-
55-
/// MO_TLSGD - Represents the offset into the global offset table at which
56-
// the module ID and TSL block offset reside during execution (General
57-
// Dynamic TLS).
58-
MO_TLSGD,
59-
60-
/// MO_TLSLDM - Represents the offset into the global offset table at which
61-
// the module ID and TSL block offset reside during execution (Local
62-
// Dynamic TLS).
63-
MO_TLSLDM,
64-
MO_DTPREL_HI,
65-
MO_DTPREL_LO,
66-
67-
/// MO_GOTTPREL - Represents the offset from the thread pointer (Initial
68-
// Exec TLS).
69-
MO_GOTTPREL,
70-
71-
/// MO_TPREL_HI/LO - Represents the hi and low part of the offset from
72-
// the thread pointer (Local Exec TLS).
73-
MO_TPREL_HI,
74-
MO_TPREL_LO,
75-
76-
// N32/64 Flags.
77-
MO_GPOFF_HI,
78-
MO_GPOFF_LO,
79-
MO_GOT_DISP,
80-
MO_GOT_PAGE,
81-
MO_GOT_OFST,
82-
83-
/// MO_HIGHER/HIGHEST - Represents the highest or higher half word of a
84-
/// 64-bit symbol address.
85-
MO_HIGHER,
86-
MO_HIGHEST,
87-
88-
/// MO_GOT_HI16/LO16, MO_CALL_HI16/LO16 - Relocations used for large GOTs.
89-
MO_GOT_HI16,
90-
MO_GOT_LO16,
91-
MO_CALL_HI16,
92-
MO_CALL_LO16,
93-
94-
/// Helper operand used to generate R_MIPS_JALR
95-
MO_JALR,
96-
97-
/// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
98-
/// reference is actually to the "__imp_FOO" symbol. This is used for
99-
/// dllimport linkage on windows.
100-
MO_DLLIMPORT = 0x20,
101-
};
102-
103-
enum {
104-
//===------------------------------------------------------------------===//
105-
// Instruction encodings. These are the standard/most common forms for
106-
// Mips instructions.
107-
//
108-
109-
// Pseudo - This represents an instruction that is a pseudo instruction
110-
// or one that has not been implemented yet. It is illegal to code generate
111-
// it, but tolerated for intermediate implementation stages.
112-
Pseudo = 0,
113-
114-
/// FrmR - This form is for instructions of the format R.
115-
FrmR = 1,
116-
/// FrmI - This form is for instructions of the format I.
117-
FrmI = 2,
118-
/// FrmJ - This form is for instructions of the format J.
119-
FrmJ = 3,
120-
/// FrmFR - This form is for instructions of the format FR.
121-
FrmFR = 4,
122-
/// FrmFI - This form is for instructions of the format FI.
123-
FrmFI = 5,
124-
/// FrmOther - This form is for instructions that have no specific format.
125-
FrmOther = 6,
126-
127-
FormMask = 15,
128-
/// IsCTI - Instruction is a Control Transfer Instruction.
129-
IsCTI = 1 << 4,
130-
/// HasForbiddenSlot - Instruction has a forbidden slot.
131-
HasForbiddenSlot = 1 << 5,
132-
/// HasFCCRegOperand - Instruction uses an $fcc<x> register.
133-
HasFCCRegOperand = 1 << 6
134-
135-
};
136-
137-
enum OperandType : unsigned {
138-
OPERAND_FIRST_MIPS_MEM_IMM = MCOI::OPERAND_FIRST_TARGET,
139-
OPERAND_MEM_SIMM9 = OPERAND_FIRST_MIPS_MEM_IMM,
140-
OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9
141-
};
142-
}
29+
/// Target Operand Flag enum.
30+
enum TOF {
31+
//===------------------------------------------------------------------===//
32+
// Mips Specific MachineOperand flags.
33+
34+
MO_NO_FLAG,
35+
36+
// Represents the offset into the global offset table at which
37+
// the address the relocation entry symbol resides during execution.
38+
MO_GOT,
39+
40+
// Represents the offset into the global offset table at
41+
// which the address of a call site relocation entry symbol resides
42+
// during execution. This is different from the above since this flag
43+
// can only be present in call instructions.
44+
MO_GOT_CALL,
45+
46+
// Represents the offset from the current gp value to be used
47+
// for the relocatable object file being produced.
48+
MO_GPREL,
49+
50+
// Represents the hi or low part of an absolute symbol
51+
// address.
52+
MO_ABS_HI,
53+
MO_ABS_LO,
54+
55+
// Represents the offset into the global offset table at which
56+
// the module ID and TSL block offset reside during execution (General
57+
// Dynamic TLS).
58+
MO_TLSGD,
59+
60+
// Represents the offset into the global offset table at which
61+
// the module ID and TSL block offset reside during execution (Local
62+
// Dynamic TLS).
63+
MO_TLSLDM,
64+
MO_DTPREL_HI,
65+
MO_DTPREL_LO,
66+
67+
// Represents the offset from the thread pointer (Initial
68+
// Exec TLS).
69+
MO_GOTTPREL,
70+
71+
// Represents the hi and low part of the offset from
72+
// the thread pointer (Local Exec TLS).
73+
MO_TPREL_HI,
74+
MO_TPREL_LO,
75+
76+
// N32/64 Flags.
77+
MO_GPOFF_HI,
78+
MO_GPOFF_LO,
79+
MO_GOT_DISP,
80+
MO_GOT_PAGE,
81+
MO_GOT_OFST,
82+
83+
// Represents the highest or higher half word of a
84+
// 64-bit symbol address.
85+
MO_HIGHER,
86+
MO_HIGHEST,
87+
88+
// Relocations used for large GOTs.
89+
MO_GOT_HI16,
90+
MO_GOT_LO16,
91+
MO_CALL_HI16,
92+
MO_CALL_LO16,
93+
94+
// Helper operand used to generate R_MIPS_JALR
95+
MO_JALR,
96+
97+
// On a symbol operand "FOO", this indicates that the
98+
// reference is actually to the "__imp_FOO" symbol. This is used for
99+
// dllimport linkage on windows.
100+
MO_DLLIMPORT = 0x20,
101+
};
102+
103+
enum {
104+
//===------------------------------------------------------------------===//
105+
// Instruction encodings. These are the standard/most common forms for
106+
// Mips instructions.
107+
//
108+
109+
// This represents an instruction that is a pseudo instruction
110+
// or one that has not been implemented yet. It is illegal to code generate
111+
// it, but tolerated for intermediate implementation stages.
112+
Pseudo = 0,
113+
114+
// This form is for instructions of the format R.
115+
FrmR = 1,
116+
// This form is for instructions of the format I.
117+
FrmI = 2,
118+
// This form is for instructions of the format J.
119+
FrmJ = 3,
120+
// This form is for instructions of the format FR.
121+
FrmFR = 4,
122+
// This form is for instructions of the format FI.
123+
FrmFI = 5,
124+
// This form is for instructions that have no specific format.
125+
FrmOther = 6,
126+
127+
FormMask = 15,
128+
// Instruction is a Control Transfer Instruction.
129+
IsCTI = 1 << 4,
130+
// Instruction has a forbidden slot.
131+
HasForbiddenSlot = 1 << 5,
132+
// Instruction uses an $fcc<x> register.
133+
HasFCCRegOperand = 1 << 6
134+
135+
};
136+
137+
enum OperandType : unsigned {
138+
OPERAND_FIRST_MIPS_MEM_IMM = MCOI::OPERAND_FIRST_TARGET,
139+
OPERAND_MEM_SIMM9 = OPERAND_FIRST_MIPS_MEM_IMM,
140+
OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9
141+
};
142+
} // namespace MipsII
143143

144144
inline static MCRegister getMSARegFromFReg(MCRegister Reg) {
145145
if (Reg >= Mips::F0 && Reg <= Mips::F31)
@@ -149,6 +149,6 @@ inline static MCRegister getMSARegFromFReg(MCRegister Reg) {
149149
else
150150
return MCRegister();
151151
}
152-
}
152+
} // namespace llvm
153153

154154
#endif

0 commit comments

Comments
 (0)