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[LV, VPlan] Check if plan is compatible to EVL transform
Vector loops generated from the EVL transform may experience issues on architectures where EVL differs from RuntimeVF at the second-to-last iteration. This patch introduces a check before applying EVL transform. If any recipes in loop rely on RuntimeVF, the vectorizer stop to generate the plan.
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4 files changed

+141
-58
lines changed

4 files changed

+141
-58
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 28 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8539,6 +8539,29 @@ VPRecipeBuilder::tryToCreateWidenRecipe(Instruction *Instr,
85398539
return tryToWiden(Instr, Operands, VPBB);
85408540
}
85418541

8542+
// EVL transform doesn't support backends where EVL diffs from RuntimeVF
8543+
// in the second-to-last iteration.
8544+
// Return false if the vector region has recipes relying on
8545+
// RuntimeVF.
8546+
static bool isCompatibleToEVLTransform(VPlan &Plan) {
8547+
auto HasAnyRuntimeVFUserInLoop = [](VPlan &Plan) -> bool {
8548+
for (auto &Phi : Plan.getVectorLoopRegion()->getEntryBasicBlock()->phis())
8549+
if (isa<VPWidenIntOrFpInductionRecipe>(&Phi) ||
8550+
isa<VPWidenPointerInductionRecipe>(&Phi))
8551+
return true;
8552+
for (VPBasicBlock *VPBB : VPBlockUtils::blocksOnly<VPBasicBlock>(
8553+
vp_depth_first_deep(Plan.getVectorLoopRegion())))
8554+
for (VPRecipeBase &Recipe : *VPBB)
8555+
if (auto *VecPtrR = dyn_cast<VPVectorPointerRecipe>(&Recipe))
8556+
if (VecPtrR->isReverse())
8557+
return true;
8558+
return false;
8559+
};
8560+
if (HasAnyRuntimeVFUserInLoop(Plan))
8561+
return false;
8562+
return true;
8563+
}
8564+
85428565
void LoopVectorizationPlanner::buildVPlansWithVPRecipes(ElementCount MinVF,
85438566
ElementCount MaxVF) {
85448567
assert(OrigLoop->isInnermost() && "Inner loop expected.");
@@ -8553,8 +8576,12 @@ void LoopVectorizationPlanner::buildVPlansWithVPRecipes(ElementCount MinVF,
85538576
*Plan, CM.getMinimalBitwidths(), PSE.getSE()->getContext());
85548577
VPlanTransforms::optimize(*Plan, *PSE.getSE());
85558578
// TODO: try to put it close to addActiveLaneMask().
8556-
if (CM.foldTailWithEVL())
8579+
if (CM.foldTailWithEVL()) {
8580+
// Don't generate plan if the plan is not EVL-compatible
8581+
if (!isCompatibleToEVLTransform(*Plan))
8582+
break;
85578583
VPlanTransforms::addExplicitVectorLength(*Plan);
8584+
}
85588585
assert(verifyVPlanIsValid(*Plan) && "VPlan is invalid");
85598586
VPlans.push_back(std::move(Plan));
85608587
}

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1576,6 +1576,7 @@ class VPVectorPointerRecipe : public VPRecipeWithIRFlags {
15761576

15771577
void execute(VPTransformState &State) override;
15781578

1579+
bool isReverse() { return IsReverse; }
15791580
bool onlyFirstLaneUsed(const VPValue *Op) const override {
15801581
assert(is_contained(operands(), Op) &&
15811582
"Op must be an operand of the recipe");

‎llvm/test/Transforms/LoopVectorize/RISCV/evl-compatible-loops.ll

Lines changed: 103 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,103 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2+
; RUN: opt -passes=loop-vectorize -force-tail-folding-style=data-with-evl \
3+
; RUN: -prefer-predicate-over-epilogue=predicate-dont-vectorize \
4+
; RUN: -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s
5+
6+
; Check loops having VPWidenIntOrFpInductionRecipe
7+
define void @foo(ptr noalias %a, i64 %N) {
8+
; CHECK-LABEL: define void @foo(
9+
; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
10+
; CHECK-NEXT: entry:
11+
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
12+
; CHECK: for.body:
13+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
14+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]]
15+
; CHECK-NEXT: store i64 [[IV]], ptr [[ARRAYIDX]], align 8
16+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
17+
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
18+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]]
19+
; CHECK: for.cond.cleanup:
20+
; CHECK-NEXT: ret void
21+
;
22+
entry:
23+
br label %for.body
24+
25+
for.body:
26+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
27+
%arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv
28+
store i64 %iv, ptr %arrayidx, align 8
29+
%iv.next = add nuw nsw i64 %iv, 1
30+
%exitcond.not = icmp eq i64 %iv.next, %N
31+
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
32+
33+
for.cond.cleanup:
34+
ret void
35+
}
36+
37+
; Check loops having VPWidenPointerInductionRecipe
38+
define void @foo2(ptr noalias %a, ptr noalias %b, i64 %N) {
39+
; CHECK-LABEL: define void @foo2(
40+
; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
41+
; CHECK-NEXT: entry:
42+
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
43+
; CHECK: for.body:
44+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
45+
; CHECK-NEXT: [[ADDR:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ], [ [[B]], [[ENTRY]] ]
46+
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[ADDR]], i64 8
47+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]]
48+
; CHECK-NEXT: store ptr [[ADDR]], ptr [[ARRAYIDX]], align 8
49+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
50+
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
51+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]]
52+
; CHECK: for.cond.cleanup:
53+
; CHECK-NEXT: ret void
54+
;
55+
entry:
56+
br label %for.body
57+
58+
for.body:
59+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
60+
%addr = phi ptr [ %incdec.ptr, %for.body ], [ %b, %entry ]
61+
%incdec.ptr = getelementptr inbounds i8, ptr %addr, i64 8
62+
%arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv
63+
store ptr %addr, ptr %arrayidx, align 8
64+
%iv.next = add nuw nsw i64 %iv, 1
65+
%exitcond.not = icmp eq i64 %iv.next, %N
66+
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
67+
68+
for.cond.cleanup:
69+
ret void
70+
}
71+
72+
; Check loops having VPVectorPointerRecipe that access in reverse order
73+
define void @foo3(ptr noalias %a, i64 %N) {
74+
; CHECK-LABEL: define void @foo3(
75+
; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
76+
; CHECK-NEXT: entry:
77+
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
78+
; CHECK: for.body:
79+
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
80+
; CHECK-NEXT: [[ADDR:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[FOR_BODY]] ], [ [[A]], [[ENTRY]] ]
81+
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[ADDR]], i64 -4
82+
; CHECK-NEXT: store i64 [[N]], ptr [[ADDR]], align 8
83+
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
84+
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
85+
; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY]]
86+
; CHECK: for.cond.cleanup:
87+
; CHECK-NEXT: ret void
88+
;
89+
entry:
90+
br label %for.body
91+
92+
for.body:
93+
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
94+
%addr = phi ptr [ %incdec.ptr, %for.body ], [ %a, %entry ]
95+
%incdec.ptr = getelementptr inbounds i8, ptr %addr, i64 -4
96+
store i64 %N, ptr %addr, align 8
97+
%iv.next = add nuw nsw i64 %iv, 1
98+
%exitcond.not = icmp eq i64 %iv.next, %N
99+
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
100+
101+
for.cond.cleanup:
102+
ret void
103+
}

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-gather-scatter.ll

Lines changed: 9 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -12,66 +12,18 @@
1212
define void @gather_scatter(ptr noalias %in, ptr noalias %out, ptr noalias %index, i64 %n) {
1313
; IF-EVL-LABEL: @gather_scatter(
1414
; IF-EVL-NEXT: entry:
15-
; IF-EVL-NEXT: [[TMP0:%.*]] = sub i64 -1, [[N:%.*]]
16-
; IF-EVL-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
17-
; IF-EVL-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 2
18-
; IF-EVL-NEXT: [[TMP3:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]]
19-
; IF-EVL-NEXT: br i1 [[TMP3]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
20-
; IF-EVL: vector.ph:
21-
; IF-EVL-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
22-
; IF-EVL-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2
23-
; IF-EVL-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
24-
; IF-EVL-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 2
25-
; IF-EVL-NEXT: [[TMP8:%.*]] = sub i64 [[TMP7]], 1
26-
; IF-EVL-NEXT: [[N_RND_UP:%.*]] = add i64 [[N]], [[TMP8]]
27-
; IF-EVL-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP5]]
28-
; IF-EVL-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
29-
; IF-EVL-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
30-
; IF-EVL-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 2
31-
; IF-EVL-NEXT: [[TMP11:%.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
32-
; IF-EVL-NEXT: [[TMP12:%.*]] = add <vscale x 2 x i64> [[TMP11]], zeroinitializer
33-
; IF-EVL-NEXT: [[TMP13:%.*]] = mul <vscale x 2 x i64> [[TMP12]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i64 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
34-
; IF-EVL-NEXT: [[INDUCTION:%.*]] = add <vscale x 2 x i64> zeroinitializer, [[TMP13]]
35-
; IF-EVL-NEXT: [[TMP14:%.*]] = call i64 @llvm.vscale.i64()
36-
; IF-EVL-NEXT: [[TMP15:%.*]] = mul i64 [[TMP14]], 2
37-
; IF-EVL-NEXT: [[TMP16:%.*]] = mul i64 1, [[TMP15]]
38-
; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP16]], i64 0
39-
; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
40-
; IF-EVL-NEXT: br label [[VECTOR_BODY:%.*]]
41-
; IF-EVL: vector.body:
42-
; IF-EVL-NEXT: [[INDEX1:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
43-
; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], [[VECTOR_BODY]] ]
44-
; IF-EVL-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[INDUCTION]], [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
45-
; IF-EVL-NEXT: [[TMP17:%.*]] = sub i64 [[N]], [[EVL_BASED_IV]]
46-
; IF-EVL-NEXT: [[TMP18:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[TMP17]], i32 2, i1 true)
47-
; IF-EVL-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[INDEX:%.*]], <vscale x 2 x i64> [[VEC_IND]]
48-
; IF-EVL-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <vscale x 2 x i64> @llvm.vp.gather.nxv2i64.nxv2p0(<vscale x 2 x ptr> align 8 [[TMP20]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer), i32 [[TMP18]])
49-
; IF-EVL-NEXT: [[TMP21:%.*]] = getelementptr inbounds float, ptr [[IN:%.*]], <vscale x 2 x i64> [[WIDE_MASKED_GATHER]]
50-
; IF-EVL-NEXT: [[WIDE_MASKED_GATHER2:%.*]] = call <vscale x 2 x float> @llvm.vp.gather.nxv2f32.nxv2p0(<vscale x 2 x ptr> align 4 [[TMP21]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer), i32 [[TMP18]])
51-
; IF-EVL-NEXT: [[TMP22:%.*]] = getelementptr inbounds float, ptr [[OUT:%.*]], <vscale x 2 x i64> [[WIDE_MASKED_GATHER]]
52-
; IF-EVL-NEXT: call void @llvm.vp.scatter.nxv2f32.nxv2p0(<vscale x 2 x float> [[WIDE_MASKED_GATHER2]], <vscale x 2 x ptr> align 4 [[TMP22]], <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i64 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer), i32 [[TMP18]])
53-
; IF-EVL-NEXT: [[TMP23:%.*]] = zext i32 [[TMP18]] to i64
54-
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP23]], [[EVL_BASED_IV]]
55-
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX1]], [[TMP10]]
56-
; IF-EVL-NEXT: [[VEC_IND_NEXT]] = add <vscale x 2 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]
57-
; IF-EVL-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
58-
; IF-EVL-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
59-
; IF-EVL: middle.block:
60-
; IF-EVL-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]]
61-
; IF-EVL: scalar.ph:
62-
; IF-EVL-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
6315
; IF-EVL-NEXT: br label [[FOR_BODY:%.*]]
6416
; IF-EVL: for.body:
65-
; IF-EVL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
66-
; IF-EVL-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[INDEX]], i64 [[INDVARS_IV]]
67-
; IF-EVL-NEXT: [[TMP25:%.*]] = load i64, ptr [[ARRAYIDX3]], align 8
68-
; IF-EVL-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[IN]], i64 [[TMP25]]
69-
; IF-EVL-NEXT: [[TMP26:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
70-
; IF-EVL-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[OUT]], i64 [[TMP25]]
71-
; IF-EVL-NEXT: store float [[TMP26]], ptr [[ARRAYIDX7]], align 4
17+
; IF-EVL-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ]
18+
; IF-EVL-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[INDEX:%.*]], i64 [[INDVARS_IV]]
19+
; IF-EVL-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX3]], align 8
20+
; IF-EVL-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[IN:%.*]], i64 [[TMP0]]
21+
; IF-EVL-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
22+
; IF-EVL-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[OUT:%.*]], i64 [[TMP0]]
23+
; IF-EVL-NEXT: store float [[TMP1]], ptr [[ARRAYIDX7]], align 4
7224
; IF-EVL-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
73-
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]]
74-
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
25+
; IF-EVL-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N:%.*]]
26+
; IF-EVL-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]]
7527
; IF-EVL: for.end:
7628
; IF-EVL-NEXT: ret void
7729
;

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