Skip to content

Commit b43712a

Browse files
rotaterightrotateright
committed
clean up tests and auto-generate checks
llvm-svn: 282896
1 parent b002f63 commit b43712a

File tree

1 file changed

+124
-56
lines changed

1 file changed

+124
-56
lines changed

‎llvm/test/Transforms/InstCombine/vector-casts.ll

Lines changed: 124 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -1,132 +1,199 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
12
; RUN: opt < %s -instcombine -S | FileCheck %s
23

34
; This turns into a&1 != 0
45
define <2 x i1> @test1(<2 x i64> %a) {
6+
; CHECK-LABEL: @test1(
7+
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> %a, <i64 1, i64 1>
8+
; CHECK-NEXT: [[T:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer
9+
; CHECK-NEXT: ret <2 x i1> [[T]]
10+
;
511
%t = trunc <2 x i64> %a to <2 x i1>
612
ret <2 x i1> %t
7-
8-
; CHECK-LABEL: @test1(
9-
; CHECK: and <2 x i64> %a, <i64 1, i64 1>
10-
; CHECK: icmp ne <2 x i64> %1, zeroinitializer
1113
}
1214

1315
; The ashr turns into an lshr.
1416
define <2 x i64> @test2(<2 x i64> %a) {
17+
; CHECK-LABEL: @test2(
18+
; CHECK-NEXT: [[B:%.*]] = and <2 x i64> %a, <i64 65535, i64 65535>
19+
; CHECK-NEXT: [[T:%.*]] = lshr <2 x i64> [[B]], <i64 1, i64 1>
20+
; CHECK-NEXT: ret <2 x i64> [[T]]
21+
;
1522
%b = and <2 x i64> %a, <i64 65535, i64 65535>
1623
%t = ashr <2 x i64> %b, <i64 1, i64 1>
1724
ret <2 x i64> %t
18-
19-
; CHECK-LABEL: @test2(
20-
; CHECK: and <2 x i64> %a, <i64 65535, i64 65535>
21-
; CHECK: lshr <2 x i64> %b, <i64 1, i64 1>
2225
}
2326

24-
25-
26-
define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) nounwind readnone {
27-
entry:
28-
%cmp = fcmp ord <4 x float> %a, zeroinitializer
29-
%sext = sext <4 x i1> %cmp to <4 x i32>
30-
%cmp4 = fcmp ord <4 x float> %b, zeroinitializer
31-
%sext5 = sext <4 x i1> %cmp4 to <4 x i32>
32-
%and = and <4 x i32> %sext, %sext5
33-
%conv = bitcast <4 x i32> %and to <2 x i64>
34-
ret <2 x i64> %conv
35-
27+
define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) {
3628
; CHECK-LABEL: @test3(
37-
; CHECK: fcmp ord <4 x float> %a, %b
38-
}
39-
40-
define <2 x i64> @test4(<4 x float> %a, <4 x float> %b) nounwind readnone {
41-
entry:
42-
%cmp = fcmp uno <4 x float> %a, zeroinitializer
43-
%sext = sext <4 x i1> %cmp to <4 x i32>
44-
%cmp4 = fcmp uno <4 x float> %b, zeroinitializer
45-
%sext5 = sext <4 x i1> %cmp4 to <4 x i32>
46-
%or = or <4 x i32> %sext, %sext5
47-
%conv = bitcast <4 x i32> %or to <2 x i64>
48-
ret <2 x i64> %conv
29+
; CHECK-NEXT: [[TMP1:%.*]] = fcmp ord <4 x float> %a, %b
30+
; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
31+
; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64>
32+
; CHECK-NEXT: ret <2 x i64> [[CONV]]
33+
;
34+
%cmp = fcmp ord <4 x float> %a, zeroinitializer
35+
%sext = sext <4 x i1> %cmp to <4 x i32>
36+
%cmp4 = fcmp ord <4 x float> %b, zeroinitializer
37+
%sext5 = sext <4 x i1> %cmp4 to <4 x i32>
38+
%and = and <4 x i32> %sext, %sext5
39+
%conv = bitcast <4 x i32> %and to <2 x i64>
40+
ret <2 x i64> %conv
41+
}
42+
43+
define <2 x i64> @test4(<4 x float> %a, <4 x float> %b) {
4944
; CHECK-LABEL: @test4(
50-
; CHECK: fcmp uno <4 x float> %a, %b
45+
; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno <4 x float> %a, %b
46+
; CHECK-NEXT: [[OR:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
47+
; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[OR]] to <2 x i64>
48+
; CHECK-NEXT: ret <2 x i64> [[CONV]]
49+
;
50+
%cmp = fcmp uno <4 x float> %a, zeroinitializer
51+
%sext = sext <4 x i1> %cmp to <4 x i32>
52+
%cmp4 = fcmp uno <4 x float> %b, zeroinitializer
53+
%sext5 = sext <4 x i1> %cmp4 to <4 x i32>
54+
%or = or <4 x i32> %sext, %sext5
55+
%conv = bitcast <4 x i32> %or to <2 x i64>
56+
ret <2 x i64> %conv
5157
}
5258

53-
5459
; rdar://7434900
55-
define <2 x i64> @test5(<4 x float> %a, <4 x float> %b) nounwind readnone {
56-
entry:
57-
%cmp = fcmp ult <4 x float> %a, zeroinitializer
58-
%sext = sext <4 x i1> %cmp to <4 x i32>
59-
%cmp4 = fcmp ult <4 x float> %b, zeroinitializer
60-
%sext5 = sext <4 x i1> %cmp4 to <4 x i32>
61-
%and = and <4 x i32> %sext, %sext5
62-
%conv = bitcast <4 x i32> %and to <2 x i64>
63-
ret <2 x i64> %conv
64-
60+
define <2 x i64> @test5(<4 x float> %a, <4 x float> %b) {
6561
; CHECK-LABEL: @test5(
66-
; CHECK: %fold.and = and <4 x i1> %cmp4, %cmp
67-
; CHECK: sext <4 x i1> %fold.and to <4 x i32>
68-
}
69-
70-
71-
define void @convert(<2 x i32>* %dst.addr, <2 x i64> %src) nounwind {
72-
entry:
62+
; CHECK-NEXT: [[CMP:%.*]] = fcmp ult <4 x float> %a, zeroinitializer
63+
; CHECK-NEXT: [[CMP4:%.*]] = fcmp ult <4 x float> %b, zeroinitializer
64+
; CHECK-NEXT: [[NARROW:%.*]] = and <4 x i1> [[CMP4]], [[CMP]]
65+
; CHECK-NEXT: [[AND:%.*]] = sext <4 x i1> [[NARROW]] to <4 x i32>
66+
; CHECK-NEXT: [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64>
67+
; CHECK-NEXT: ret <2 x i64> [[CONV]]
68+
;
69+
%cmp = fcmp ult <4 x float> %a, zeroinitializer
70+
%sext = sext <4 x i1> %cmp to <4 x i32>
71+
%cmp4 = fcmp ult <4 x float> %b, zeroinitializer
72+
%sext5 = sext <4 x i1> %cmp4 to <4 x i32>
73+
%and = and <4 x i32> %sext, %sext5
74+
%conv = bitcast <4 x i32> %and to <2 x i64>
75+
ret <2 x i64> %conv
76+
}
77+
78+
define void @convert(<2 x i32>* %dst.addr, <2 x i64> %src) {
79+
; CHECK-LABEL: @convert(
80+
; CHECK-NEXT: [[VAL:%.*]] = trunc <2 x i64> %src to <2 x i32>
81+
; CHECK-NEXT: [[ADD:%.*]] = add <2 x i32> [[VAL]], <i32 1, i32 1>
82+
; CHECK-NEXT: store <2 x i32> [[ADD]], <2 x i32>* %dst.addr, align 8
83+
; CHECK-NEXT: ret void
84+
;
7385
%val = trunc <2 x i64> %src to <2 x i32>
7486
%add = add <2 x i32> %val, <i32 1, i32 1>
7587
store <2 x i32> %add, <2 x i32>* %dst.addr
7688
ret void
7789
}
7890

7991
define <2 x i65> @foo(<2 x i64> %t) {
92+
; CHECK-LABEL: @foo(
93+
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> %t, <i64 4294967295, i64 4294967295>
94+
; CHECK-NEXT: [[B:%.*]] = zext <2 x i64> [[TMP1]] to <2 x i65>
95+
; CHECK-NEXT: ret <2 x i65> [[B]]
96+
;
8097
%a = trunc <2 x i64> %t to <2 x i32>
8198
%b = zext <2 x i32> %a to <2 x i65>
8299
ret <2 x i65> %b
83100
}
101+
84102
define <2 x i64> @bar(<2 x i65> %t) {
103+
; CHECK-LABEL: @bar(
104+
; CHECK-NEXT: [[A:%.*]] = trunc <2 x i65> %t to <2 x i64>
105+
; CHECK-NEXT: [[B:%.*]] = and <2 x i64> [[A]], <i64 4294967295, i64 4294967295>
106+
; CHECK-NEXT: ret <2 x i64> [[B]]
107+
;
85108
%a = trunc <2 x i65> %t to <2 x i32>
86109
%b = zext <2 x i32> %a to <2 x i64>
87110
ret <2 x i64> %b
88111
}
112+
89113
define <2 x i65> @foos(<2 x i64> %t) {
114+
; CHECK-LABEL: @foos(
115+
; CHECK-NEXT: [[A:%.*]] = zext <2 x i64> %t to <2 x i65>
116+
; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i65> [[A]], <i65 33, i65 33>
117+
; CHECK-NEXT: [[B:%.*]] = ashr <2 x i65> [[SEXT]], <i65 33, i65 33>
118+
; CHECK-NEXT: ret <2 x i65> [[B]]
119+
;
90120
%a = trunc <2 x i64> %t to <2 x i32>
91121
%b = sext <2 x i32> %a to <2 x i65>
92122
ret <2 x i65> %b
93123
}
124+
94125
define <2 x i64> @bars(<2 x i65> %t) {
126+
; CHECK-LABEL: @bars(
127+
; CHECK-NEXT: [[A:%.*]] = trunc <2 x i65> %t to <2 x i64>
128+
; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[A]], <i64 32, i64 32>
129+
; CHECK-NEXT: [[B:%.*]] = ashr <2 x i64> [[SEXT]], <i64 32, i64 32>
130+
; CHECK-NEXT: ret <2 x i64> [[B]]
131+
;
95132
%a = trunc <2 x i65> %t to <2 x i32>
96133
%b = sext <2 x i32> %a to <2 x i64>
97134
ret <2 x i64> %b
98135
}
136+
99137
define <2 x i64> @quxs(<2 x i64> %t) {
138+
; CHECK-LABEL: @quxs(
139+
; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> %t, <i64 32, i64 32>
140+
; CHECK-NEXT: [[B:%.*]] = ashr <2 x i64> [[SEXT]], <i64 32, i64 32>
141+
; CHECK-NEXT: ret <2 x i64> [[B]]
142+
;
100143
%a = trunc <2 x i64> %t to <2 x i32>
101144
%b = sext <2 x i32> %a to <2 x i64>
102145
ret <2 x i64> %b
103146
}
147+
104148
define <2 x i64> @quxt(<2 x i64> %t) {
149+
; CHECK-LABEL: @quxt(
150+
; CHECK-NEXT: [[A:%.*]] = shl <2 x i64> %t, <i64 32, i64 32>
151+
; CHECK-NEXT: [[B:%.*]] = ashr <2 x i64> [[A]], <i64 32, i64 32>
152+
; CHECK-NEXT: ret <2 x i64> [[B]]
153+
;
105154
%a = shl <2 x i64> %t, <i64 32, i64 32>
106155
%b = ashr <2 x i64> %a, <i64 32, i64 32>
107156
ret <2 x i64> %b
108157
}
158+
109159
define <2 x double> @fa(<2 x double> %t) {
160+
; CHECK-LABEL: @fa(
161+
; CHECK-NEXT: [[A:%.*]] = fptrunc <2 x double> %t to <2 x float>
162+
; CHECK-NEXT: [[B:%.*]] = fpext <2 x float> [[A]] to <2 x double>
163+
; CHECK-NEXT: ret <2 x double> [[B]]
164+
;
110165
%a = fptrunc <2 x double> %t to <2 x float>
111166
%b = fpext <2 x float> %a to <2 x double>
112167
ret <2 x double> %b
113168
}
169+
114170
define <2 x double> @fb(<2 x double> %t) {
171+
; CHECK-LABEL: @fb(
172+
; CHECK-NEXT: [[A:%.*]] = fptoui <2 x double> %t to <2 x i64>
173+
; CHECK-NEXT: [[B:%.*]] = uitofp <2 x i64> [[A]] to <2 x double>
174+
; CHECK-NEXT: ret <2 x double> [[B]]
175+
;
115176
%a = fptoui <2 x double> %t to <2 x i64>
116177
%b = uitofp <2 x i64> %a to <2 x double>
117178
ret <2 x double> %b
118179
}
180+
119181
define <2 x double> @fc(<2 x double> %t) {
182+
; CHECK-LABEL: @fc(
183+
; CHECK-NEXT: [[A:%.*]] = fptosi <2 x double> %t to <2 x i64>
184+
; CHECK-NEXT: [[B:%.*]] = sitofp <2 x i64> [[A]] to <2 x double>
185+
; CHECK-NEXT: ret <2 x double> [[B]]
186+
;
120187
%a = fptosi <2 x double> %t to <2 x i64>
121188
%b = sitofp <2 x i64> %a to <2 x double>
122189
ret <2 x double> %b
123190
}
124191

125192
; PR9228
126-
; This was a crasher, so no CHECK statements.
127-
define <4 x float> @f(i32 %a) nounwind alwaysinline {
193+
define <4 x float> @f(i32 %a) {
128194
; CHECK-LABEL: @f(
129-
entry:
195+
; CHECK-NEXT: ret <4 x float> undef
196+
;
130197
%dim = insertelement <4 x i32> undef, i32 %a, i32 0
131198
%dim30 = insertelement <4 x i32> %dim, i32 %a, i32 1
132199
%dim31 = insertelement <4 x i32> %dim30, i32 %a, i32 2
@@ -150,13 +217,14 @@ entry:
150217
}
151218

152219
define <8 x i32> @pr24458(<8 x float> %n) {
153-
; CHECK-LABEL: @pr24458
220+
; CHECK-LABEL: @pr24458(
221+
; CHECK-NEXT: ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
222+
;
154223
%notequal_b_load_.i = fcmp une <8 x float> %n, zeroinitializer
155224
%equal_a_load72_.i = fcmp ueq <8 x float> %n, zeroinitializer
156225
%notequal_b_load__to_boolvec.i = sext <8 x i1> %notequal_b_load_.i to <8 x i32>
157226
%equal_a_load72__to_boolvec.i = sext <8 x i1> %equal_a_load72_.i to <8 x i32>
158227
%wrong = or <8 x i32> %notequal_b_load__to_boolvec.i, %equal_a_load72__to_boolvec.i
159228
ret <8 x i32> %wrong
160-
; CHECK-NEXT: ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
161229
}
162230

0 commit comments

Comments
 (0)