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[RISCV][test] Add tests for subtraction if above a constant threshold
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‎llvm/test/CodeGen/RISCV/rv32zbb.ll

Lines changed: 138 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1718,3 +1718,141 @@ define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 %x, i32 %y, ptr %z) {
17181718
%sub = sub nuw i32 %x, %select
17191719
ret i32 %sub
17201720
}
1721+
1722+
define i8 @sub_if_uge_C_i8(i8 zeroext %x) {
1723+
; CHECK-LABEL: sub_if_uge_C_i8:
1724+
; CHECK: # %bb.0:
1725+
; CHECK-NEXT: sltiu a1, a0, 13
1726+
; CHECK-NEXT: addi a1, a1, -1
1727+
; CHECK-NEXT: andi a1, a1, -13
1728+
; CHECK-NEXT: add a0, a0, a1
1729+
; CHECK-NEXT: ret
1730+
%cmp = icmp ugt i8 %x, 12
1731+
%sub = add i8 %x, -13
1732+
%conv4 = select i1 %cmp, i8 %sub, i8 %x
1733+
ret i8 %conv4
1734+
}
1735+
1736+
define i16 @sub_if_uge_C_i16(i16 zeroext %x) {
1737+
; CHECK-LABEL: sub_if_uge_C_i16:
1738+
; CHECK: # %bb.0:
1739+
; CHECK-NEXT: sltiu a1, a0, 251
1740+
; CHECK-NEXT: addi a1, a1, -1
1741+
; CHECK-NEXT: andi a1, a1, -251
1742+
; CHECK-NEXT: add a0, a0, a1
1743+
; CHECK-NEXT: ret
1744+
%cmp = icmp ugt i16 %x, 250
1745+
%sub = add i16 %x, -251
1746+
%conv4 = select i1 %cmp, i16 %sub, i16 %x
1747+
ret i16 %conv4
1748+
}
1749+
1750+
define i32 @sub_if_uge_C_i32(i32 signext %x) {
1751+
; CHECK-LABEL: sub_if_uge_C_i32:
1752+
; CHECK: # %bb.0:
1753+
; CHECK-NEXT: lui a1, 16
1754+
; CHECK-NEXT: lui a2, 1048560
1755+
; CHECK-NEXT: addi a1, a1, -16
1756+
; CHECK-NEXT: sltu a1, a1, a0
1757+
; CHECK-NEXT: neg a1, a1
1758+
; CHECK-NEXT: addi a2, a2, 15
1759+
; CHECK-NEXT: and a1, a1, a2
1760+
; CHECK-NEXT: add a0, a0, a1
1761+
; CHECK-NEXT: ret
1762+
%cmp = icmp ugt i32 %x, 65520
1763+
%sub = add i32 %x, -65521
1764+
%cond = select i1 %cmp, i32 %sub, i32 %x
1765+
ret i32 %cond
1766+
}
1767+
1768+
define i64 @sub_if_uge_C_i64(i64 %x) {
1769+
; CHECK-LABEL: sub_if_uge_C_i64:
1770+
; CHECK: # %bb.0:
1771+
; CHECK-NEXT: li a2, 1
1772+
; CHECK-NEXT: beq a1, a2, .LBB60_2
1773+
; CHECK-NEXT: # %bb.1:
1774+
; CHECK-NEXT: sltiu a2, a1, 2
1775+
; CHECK-NEXT: xori a2, a2, 1
1776+
; CHECK-NEXT: j .LBB60_3
1777+
; CHECK-NEXT: .LBB60_2:
1778+
; CHECK-NEXT: lui a2, 172127
1779+
; CHECK-NEXT: addi a2, a2, 511
1780+
; CHECK-NEXT: sltu a2, a2, a0
1781+
; CHECK-NEXT: .LBB60_3:
1782+
; CHECK-NEXT: neg a2, a2
1783+
; CHECK-NEXT: andi a3, a2, -2
1784+
; CHECK-NEXT: add a1, a1, a3
1785+
; CHECK-NEXT: lui a3, 876449
1786+
; CHECK-NEXT: addi a3, a3, -512
1787+
; CHECK-NEXT: and a2, a2, a3
1788+
; CHECK-NEXT: add a2, a0, a2
1789+
; CHECK-NEXT: sltu a0, a2, a0
1790+
; CHECK-NEXT: add a1, a1, a0
1791+
; CHECK-NEXT: mv a0, a2
1792+
; CHECK-NEXT: ret
1793+
%cmp = icmp ugt i64 %x, 4999999999
1794+
%sub = add i64 %x, -5000000000
1795+
%cond = select i1 %cmp, i64 %sub, i64 %x
1796+
ret i64 %cond
1797+
}
1798+
1799+
define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
1800+
; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32:
1801+
; CHECK: # %bb.0:
1802+
; CHECK-NEXT: lui a2, 16
1803+
; CHECK-NEXT: lui a3, 1048560
1804+
; CHECK-NEXT: addi a2, a2, -16
1805+
; CHECK-NEXT: sltu a2, a2, a0
1806+
; CHECK-NEXT: neg a4, a2
1807+
; CHECK-NEXT: addi a3, a3, 15
1808+
; CHECK-NEXT: and a3, a4, a3
1809+
; CHECK-NEXT: add a0, a0, a3
1810+
; CHECK-NEXT: sw a2, 0(a1)
1811+
; CHECK-NEXT: ret
1812+
%cmp = icmp ugt i32 %x, 65520
1813+
%conv = zext i1 %cmp to i32
1814+
store i32 %conv, ptr %z, align 4
1815+
%sub = add i32 %x, -65521
1816+
%cond = select i1 %cmp, i32 %sub, i32 %x
1817+
ret i32 %cond
1818+
}
1819+
1820+
define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
1821+
; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32:
1822+
; CHECK: # %bb.0:
1823+
; CHECK-NEXT: lui a2, 1048560
1824+
; CHECK-NEXT: lui a3, 16
1825+
; CHECK-NEXT: addi a2, a2, 15
1826+
; CHECK-NEXT: add a2, a0, a2
1827+
; CHECK-NEXT: addi a3, a3, -16
1828+
; CHECK-NEXT: sw a2, 0(a1)
1829+
; CHECK-NEXT: bltu a3, a0, .LBB62_2
1830+
; CHECK-NEXT: # %bb.1:
1831+
; CHECK-NEXT: mv a2, a0
1832+
; CHECK-NEXT: .LBB62_2:
1833+
; CHECK-NEXT: mv a0, a2
1834+
; CHECK-NEXT: ret
1835+
%sub = add i32 %x, -65521
1836+
store i32 %sub, ptr %z, align 4
1837+
%cmp = icmp ugt i32 %x, 65520
1838+
%cond = select i1 %cmp, i32 %sub, i32 %x
1839+
ret i32 %cond
1840+
}
1841+
1842+
define i32 @sub_if_uge_C_swapped_i32(i32 %x) {
1843+
; CHECK-LABEL: sub_if_uge_C_swapped_i32:
1844+
; CHECK: # %bb.0:
1845+
; CHECK-NEXT: lui a1, 16
1846+
; CHECK-NEXT: lui a2, 1048560
1847+
; CHECK-NEXT: addi a1, a1, -15
1848+
; CHECK-NEXT: sltu a1, a0, a1
1849+
; CHECK-NEXT: addi a1, a1, -1
1850+
; CHECK-NEXT: addi a2, a2, 15
1851+
; CHECK-NEXT: and a1, a1, a2
1852+
; CHECK-NEXT: add a0, a0, a1
1853+
; CHECK-NEXT: ret
1854+
%cmp = icmp ult i32 %x, 65521
1855+
%sub = add i32 %x, -65521
1856+
%cond = select i1 %cmp, i32 %x, i32 %sub
1857+
ret i32 %cond
1858+
}

‎llvm/test/CodeGen/RISCV/rv64zbb.ll

Lines changed: 128 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1884,3 +1884,131 @@ define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 signext %x, i32 signext %y, pt
18841884
%sub = sub nuw i32 %x, %select
18851885
ret i32 %sub
18861886
}
1887+
1888+
define i8 @sub_if_uge_C_i8(i8 zeroext %x) {
1889+
; CHECK-LABEL: sub_if_uge_C_i8:
1890+
; CHECK: # %bb.0:
1891+
; CHECK-NEXT: sltiu a1, a0, 13
1892+
; CHECK-NEXT: addi a1, a1, -1
1893+
; CHECK-NEXT: andi a1, a1, -13
1894+
; CHECK-NEXT: add a0, a0, a1
1895+
; CHECK-NEXT: ret
1896+
%cmp = icmp ugt i8 %x, 12
1897+
%sub = add i8 %x, -13
1898+
%conv4 = select i1 %cmp, i8 %sub, i8 %x
1899+
ret i8 %conv4
1900+
}
1901+
1902+
define i16 @sub_if_uge_C_i16(i16 zeroext %x) {
1903+
; CHECK-LABEL: sub_if_uge_C_i16:
1904+
; CHECK: # %bb.0:
1905+
; CHECK-NEXT: sltiu a1, a0, 251
1906+
; CHECK-NEXT: addi a1, a1, -1
1907+
; CHECK-NEXT: andi a1, a1, -251
1908+
; CHECK-NEXT: add a0, a0, a1
1909+
; CHECK-NEXT: ret
1910+
%cmp = icmp ugt i16 %x, 250
1911+
%sub = add i16 %x, -251
1912+
%conv4 = select i1 %cmp, i16 %sub, i16 %x
1913+
ret i16 %conv4
1914+
}
1915+
1916+
define i32 @sub_if_uge_C_i32(i32 signext %x) {
1917+
; CHECK-LABEL: sub_if_uge_C_i32:
1918+
; CHECK: # %bb.0:
1919+
; CHECK-NEXT: lui a1, 16
1920+
; CHECK-NEXT: lui a2, 1048560
1921+
; CHECK-NEXT: addiw a1, a1, -16
1922+
; CHECK-NEXT: sltu a1, a1, a0
1923+
; CHECK-NEXT: negw a1, a1
1924+
; CHECK-NEXT: addi a2, a2, 15
1925+
; CHECK-NEXT: and a1, a1, a2
1926+
; CHECK-NEXT: addw a0, a0, a1
1927+
; CHECK-NEXT: ret
1928+
%cmp = icmp ugt i32 %x, 65520
1929+
%sub = add i32 %x, -65521
1930+
%cond = select i1 %cmp, i32 %sub, i32 %x
1931+
ret i32 %cond
1932+
}
1933+
1934+
define i64 @sub_if_uge_C_i64(i64 %x) {
1935+
; CHECK-LABEL: sub_if_uge_C_i64:
1936+
; CHECK: # %bb.0:
1937+
; CHECK-NEXT: lui a1, 298
1938+
; CHECK-NEXT: lui a2, 1046192
1939+
; CHECK-NEXT: addiw a1, a1, 95
1940+
; CHECK-NEXT: addiw a2, a2, -761
1941+
; CHECK-NEXT: slli a1, a1, 12
1942+
; CHECK-NEXT: addi a1, a1, 511
1943+
; CHECK-NEXT: sltu a1, a1, a0
1944+
; CHECK-NEXT: neg a1, a1
1945+
; CHECK-NEXT: slli a2, a2, 9
1946+
; CHECK-NEXT: and a1, a1, a2
1947+
; CHECK-NEXT: add a0, a0, a1
1948+
; CHECK-NEXT: ret
1949+
%cmp = icmp ugt i64 %x, 4999999999
1950+
%sub = add i64 %x, -5000000000
1951+
%cond = select i1 %cmp, i64 %sub, i64 %x
1952+
ret i64 %cond
1953+
}
1954+
1955+
define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) {
1956+
; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32:
1957+
; CHECK: # %bb.0:
1958+
; CHECK-NEXT: lui a2, 16
1959+
; CHECK-NEXT: lui a3, 1048560
1960+
; CHECK-NEXT: addiw a2, a2, -16
1961+
; CHECK-NEXT: sltu a2, a2, a0
1962+
; CHECK-NEXT: negw a4, a2
1963+
; CHECK-NEXT: addi a3, a3, 15
1964+
; CHECK-NEXT: and a3, a4, a3
1965+
; CHECK-NEXT: addw a0, a0, a3
1966+
; CHECK-NEXT: sw a2, 0(a1)
1967+
; CHECK-NEXT: ret
1968+
%cmp = icmp ugt i32 %x, 65520
1969+
%conv = zext i1 %cmp to i32
1970+
store i32 %conv, ptr %z, align 4
1971+
%sub = add i32 %x, -65521
1972+
%cond = select i1 %cmp, i32 %sub, i32 %x
1973+
ret i32 %cond
1974+
}
1975+
1976+
define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
1977+
; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32:
1978+
; CHECK: # %bb.0:
1979+
; CHECK-NEXT: lui a2, 1048560
1980+
; CHECK-NEXT: lui a3, 16
1981+
; CHECK-NEXT: addi a2, a2, 15
1982+
; CHECK-NEXT: addw a2, a0, a2
1983+
; CHECK-NEXT: addiw a3, a3, -16
1984+
; CHECK-NEXT: sw a2, 0(a1)
1985+
; CHECK-NEXT: bltu a3, a0, .LBB75_2
1986+
; CHECK-NEXT: # %bb.1:
1987+
; CHECK-NEXT: mv a2, a0
1988+
; CHECK-NEXT: .LBB75_2:
1989+
; CHECK-NEXT: mv a0, a2
1990+
; CHECK-NEXT: ret
1991+
%sub = add i32 %x, -65521
1992+
store i32 %sub, ptr %z, align 4
1993+
%cmp = icmp ugt i32 %x, 65520
1994+
%cond = select i1 %cmp, i32 %sub, i32 %x
1995+
ret i32 %cond
1996+
}
1997+
1998+
define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) {
1999+
; CHECK-LABEL: sub_if_uge_C_swapped_i32:
2000+
; CHECK: # %bb.0:
2001+
; CHECK-NEXT: lui a1, 16
2002+
; CHECK-NEXT: lui a2, 1048560
2003+
; CHECK-NEXT: addiw a1, a1, -15
2004+
; CHECK-NEXT: sltu a1, a0, a1
2005+
; CHECK-NEXT: addi a1, a1, -1
2006+
; CHECK-NEXT: addi a2, a2, 15
2007+
; CHECK-NEXT: and a1, a1, a2
2008+
; CHECK-NEXT: addw a0, a0, a1
2009+
; CHECK-NEXT: ret
2010+
%cmp = icmp ult i32 %x, 65521
2011+
%sub = add i32 %x, -65521
2012+
%cond = select i1 %cmp, i32 %x, i32 %sub
2013+
ret i32 %cond
2014+
}

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