Skip to content

Commit b4adce0

Browse files
4vtomat4vtomat
authored
[RISCV] Tuple intrinsics are creating overly aligned memory operands (#115804)
The alignment should be same as its element type.
1 parent 9ae21b0 commit b4adce0

File tree

3 files changed

+80
-5
lines changed

3 files changed

+80
-5
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1623,10 +1623,17 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
16231623
MemTy = MemTy->getScalarType();
16241624

16251625
Info.memVT = getValueType(DL, MemTy);
1626-
if (MemTy->isTargetExtTy())
1626+
if (MemTy->isTargetExtTy()) {
1627+
// RISC-V vector tuple type's alignment type should be its element type.
1628+
if (cast<TargetExtType>(MemTy)->getName() == "riscv.vector.tuple")
1629+
MemTy = Type::getIntNTy(
1630+
MemTy->getContext(),
1631+
1 << cast<ConstantInt>(I.getArgOperand(I.arg_size() - 1))
1632+
->getZExtValue());
16271633
Info.align = DL.getABITypeAlign(MemTy);
1628-
else
1634+
} else {
16291635
Info.align = Align(DL.getTypeSizeInBits(MemTy->getScalarType()) / 8);
1636+
}
16301637
Info.size = MemoryLocation::UnknownSize;
16311638
Info.flags |=
16321639
IsStore ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;

‎llvm/test/CodeGen/RISCV/rvv/vector-tuple-align.ll

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,68 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
; RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel -target-abi=lp64 < %s | FileCheck %s
3+
4+
declare target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2), ptr , i64, i64)
5+
6+
define target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg_nxv8i8(ptr %p, i64 %vl) {
7+
; CHECK-LABEL: name: test_vlseg_nxv8i8
8+
; CHECK: bb.0.entry:
9+
; CHECK-NEXT: liveins: $x10, $x11
10+
; CHECK-NEXT: {{ $}}
11+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
12+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
13+
; CHECK-NEXT: [[PseudoVLSEG2E8_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E8_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 1)
14+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY [[PseudoVLSEG2E8_V_M1_]]
15+
; CHECK-NEXT: $v8_v9 = COPY [[COPY2]]
16+
; CHECK-NEXT: PseudoRET implicit $v8_v9
17+
entry:
18+
%0 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) undef, ptr %p, i64 %vl, i64 3)
19+
ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
20+
}
21+
22+
define target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg_nxv4i16(ptr %p, i64 %vl) {
23+
; CHECK-LABEL: name: test_vlseg_nxv4i16
24+
; CHECK: bb.0.entry:
25+
; CHECK-NEXT: liveins: $x10, $x11
26+
; CHECK-NEXT: {{ $}}
27+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
28+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
29+
; CHECK-NEXT: [[PseudoVLSEG2E16_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E16_V_M1 $noreg, [[COPY1]], [[COPY]], 4 /* e16 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 2)
30+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY [[PseudoVLSEG2E16_V_M1_]]
31+
; CHECK-NEXT: $v8_v9 = COPY [[COPY2]]
32+
; CHECK-NEXT: PseudoRET implicit $v8_v9
33+
entry:
34+
%0 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) undef, ptr %p, i64 %vl, i64 4)
35+
ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
36+
}
37+
38+
define target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg_nxv2i32(ptr %p, i64 %vl) {
39+
; CHECK-LABEL: name: test_vlseg_nxv2i32
40+
; CHECK: bb.0.entry:
41+
; CHECK-NEXT: liveins: $x10, $x11
42+
; CHECK-NEXT: {{ $}}
43+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
44+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
45+
; CHECK-NEXT: [[PseudoVLSEG2E32_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E32_V_M1 $noreg, [[COPY1]], [[COPY]], 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 4)
46+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY [[PseudoVLSEG2E32_V_M1_]]
47+
; CHECK-NEXT: $v8_v9 = COPY [[COPY2]]
48+
; CHECK-NEXT: PseudoRET implicit $v8_v9
49+
entry:
50+
%0 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) undef, ptr %p, i64 %vl, i64 5)
51+
ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
52+
}
53+
54+
define target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @test_vlseg_nxv1i64(ptr %p, i64 %vl) {
55+
; CHECK-LABEL: name: test_vlseg_nxv1i64
56+
; CHECK: bb.0.entry:
57+
; CHECK-NEXT: liveins: $x10, $x11
58+
; CHECK-NEXT: {{ $}}
59+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
60+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
61+
; CHECK-NEXT: [[PseudoVLSEG2E64_V_M1_:%[0-9]+]]:vrn2m1 = PseudoVLSEG2E64_V_M1 $noreg, [[COPY1]], [[COPY]], 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size from %ir.p, align 8)
62+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY [[PseudoVLSEG2E64_V_M1_]]
63+
; CHECK-NEXT: $v8_v9 = COPY [[COPY2]]
64+
; CHECK-NEXT: PseudoRET implicit $v8_v9
65+
entry:
66+
%0 = call target("riscv.vector.tuple", <vscale x 8 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv8i8_2t(target("riscv.vector.tuple", <vscale x 8 x i8>, 2) undef, ptr %p, i64 %vl, i64 6)
67+
ret target("riscv.vector.tuple", <vscale x 8 x i8>, 2) %0
68+
}

‎llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ define i64 @test_vlseg2ff_nxv8i8(ptr %base, i64 %vl, ptr %outvl) {
6666
; CHECK-NEXT: {{ $}}
6767
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
6868
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
69-
; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_:%[0-9]+]]:vrn2m1, [[PseudoVLSEG2E8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from %ir.base, align 16)
69+
; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_:%[0-9]+]]:vrn2m1, [[PseudoVLSEG2E8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from %ir.base, align 1)
7070
; CHECK-NEXT: $x10 = COPY [[PseudoVLSEG2E8FF_V_M1_1]]
7171
; CHECK-NEXT: PseudoRET implicit $x10
7272
entry:
@@ -83,7 +83,7 @@ define i64 @test_vlseg2ff_nxv8i8_tu(target("riscv.vector.tuple", <vscale x 8 x i
8383
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
8484
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
8585
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrn2m1 = COPY $v8_v9
86-
; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_:%[0-9]+]]:vrn2m1, [[PseudoVLSEG2E8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1 [[COPY2]], [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from %ir.base, align 16)
86+
; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_:%[0-9]+]]:vrn2m1, [[PseudoVLSEG2E8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1 [[COPY2]], [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from %ir.base, align 1)
8787
; CHECK-NEXT: $x10 = COPY [[PseudoVLSEG2E8FF_V_M1_1]]
8888
; CHECK-NEXT: PseudoRET implicit $x10
8989
entry:
@@ -102,7 +102,7 @@ define i64 @test_vlseg2ff_nxv8i8_mask(target("riscv.vector.tuple", <vscale x 8 x
102102
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
103103
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrn2m1nov0 = COPY $v8_v9
104104
; CHECK-NEXT: $v0 = COPY [[COPY1]]
105-
; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_MASK:%[0-9]+]]:vrn2m1nov0, [[PseudoVLSEG2E8FF_V_M1_MASK1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vl :: (load unknown-size from %ir.base, align 16)
105+
; CHECK-NEXT: [[PseudoVLSEG2E8FF_V_M1_MASK:%[0-9]+]]:vrn2m1nov0, [[PseudoVLSEG2E8FF_V_M1_MASK1:%[0-9]+]]:gpr = PseudoVLSEG2E8FF_V_M1_MASK [[COPY3]], [[COPY2]], $v0, [[COPY]], 3 /* e8 */, 0 /* tu, mu */, implicit-def dead $vl :: (load unknown-size from %ir.base, align 1)
106106
; CHECK-NEXT: $x10 = COPY [[PseudoVLSEG2E8FF_V_M1_MASK1]]
107107
; CHECK-NEXT: PseudoRET implicit $x10
108108
entry:

0 commit comments

Comments
 (0)