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Pierre-vhPierre-vh
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[AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128
There's quite a few opcodes that do not care about the exact AS of the pointer, just its size. Adding generic types for these will help reduce duplication in the rule definitions. I also moved the usual B types to use the new `isAnyPtr` helper I added to make sure they're supersets of the `Ptr` cases
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+77
-13
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3 files changed

+77
-13
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp

Lines changed: 33 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -605,17 +605,23 @@ LLT RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
605605
case VgprB32:
606606
case UniInVgprB32:
607607
if (Ty == LLT::scalar(32) || Ty == LLT::fixed_vector(2, 16) ||
608-
Ty == LLT::pointer(3, 32) || Ty == LLT::pointer(5, 32) ||
609-
Ty == LLT::pointer(6, 32))
608+
isAnyPtr(Ty, 32))
610609
return Ty;
611610
return LLT();
611+
case SgprPtr32:
612+
case VgprPtr32:
613+
return isAnyPtr(Ty, 32) ? Ty : LLT();
614+
case SgprPtr64:
615+
case VgprPtr64:
616+
return isAnyPtr(Ty, 64) ? Ty : LLT();
617+
case SgprPtr128:
618+
case VgprPtr128:
619+
return isAnyPtr(Ty, 128) ? Ty : LLT();
612620
case SgprB64:
613621
case VgprB64:
614622
case UniInVgprB64:
615623
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
616-
Ty == LLT::fixed_vector(4, 16) || Ty == LLT::pointer(0, 64) ||
617-
Ty == LLT::pointer(1, 64) || Ty == LLT::pointer(4, 64) ||
618-
(Ty.isPointer() && Ty.getAddressSpace() > AMDGPUAS::MAX_AMDGPU_ADDRESS))
624+
Ty == LLT::fixed_vector(4, 16) || isAnyPtr(Ty, 64))
619625
return Ty;
620626
return LLT();
621627
case SgprB96:
@@ -629,7 +635,7 @@ LLT RegBankLegalizeHelper::getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty) {
629635
case VgprB128:
630636
case UniInVgprB128:
631637
if (Ty == LLT::scalar(128) || Ty == LLT::fixed_vector(4, 32) ||
632-
Ty == LLT::fixed_vector(2, 64))
638+
Ty == LLT::fixed_vector(2, 64) || isAnyPtr(Ty, 128))
633639
return Ty;
634640
return LLT();
635641
case SgprB256:
@@ -668,6 +674,9 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
668674
case SgprP5:
669675
case SgprP6:
670676
case SgprP8:
677+
case SgprPtr32:
678+
case SgprPtr64:
679+
case SgprPtr128:
671680
case SgprV2S16:
672681
case SgprV2S32:
673682
case SgprV4S32:
@@ -705,6 +714,9 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
705714
case VgprP5:
706715
case VgprP6:
707716
case VgprP8:
717+
case VgprPtr32:
718+
case VgprPtr64:
719+
case VgprPtr128:
708720
case VgprV2S16:
709721
case VgprV2S32:
710722
case VgprV4S32:
@@ -778,12 +790,18 @@ void RegBankLegalizeHelper::applyMappingDst(
778790
case SgprB128:
779791
case SgprB256:
780792
case SgprB512:
793+
case SgprPtr32:
794+
case SgprPtr64:
795+
case SgprPtr128:
781796
case VgprB32:
782797
case VgprB64:
783798
case VgprB96:
784799
case VgprB128:
785800
case VgprB256:
786-
case VgprB512: {
801+
case VgprB512:
802+
case VgprPtr32:
803+
case VgprPtr64:
804+
case VgprPtr128: {
787805
assert(Ty == getBTyFromID(MethodIDs[OpIdx], Ty));
788806
assert(RB == getRegBankFromID(MethodIDs[OpIdx]));
789807
break;
@@ -892,7 +910,10 @@ void RegBankLegalizeHelper::applyMappingSrc(
892910
case SgprB96:
893911
case SgprB128:
894912
case SgprB256:
895-
case SgprB512: {
913+
case SgprB512:
914+
case SgprPtr32:
915+
case SgprPtr64:
916+
case SgprPtr128: {
896917
assert(Ty == getBTyFromID(MethodIDs[i], Ty));
897918
assert(RB == getRegBankFromID(MethodIDs[i]));
898919
break;
@@ -926,7 +947,10 @@ void RegBankLegalizeHelper::applyMappingSrc(
926947
case VgprB96:
927948
case VgprB128:
928949
case VgprB256:
929-
case VgprB512: {
950+
case VgprB512:
951+
case VgprPtr32:
952+
case VgprPtr64:
953+
case VgprPtr128: {
930954
assert(Ty == getBTyFromID(MethodIDs[i], Ty));
931955
if (RB != VgprRB) {
932956
auto CopyToVgpr = B.buildCopy({VgprRB, Ty}, Reg);

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

Lines changed: 25 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,10 @@
2626
using namespace llvm;
2727
using namespace AMDGPU;
2828

29+
bool AMDGPU::isAnyPtr(LLT Ty, unsigned Width) {
30+
return Ty.isPointer() && Ty.getSizeInBits() == Width;
31+
}
32+
2933
RegBankLLTMapping::RegBankLLTMapping(
3034
std::initializer_list<RegBankLLTMappingApplyID> DstOpMappingList,
3135
std::initializer_list<RegBankLLTMappingApplyID> SrcOpMappingList,
@@ -68,6 +72,12 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
6872
return MRI.getType(Reg) == LLT::pointer(6, 32);
6973
case P8:
7074
return MRI.getType(Reg) == LLT::pointer(8, 128);
75+
case Ptr32:
76+
return isAnyPtr(MRI.getType(Reg), 32);
77+
case Ptr64:
78+
return isAnyPtr(MRI.getType(Reg), 64);
79+
case Ptr128:
80+
return isAnyPtr(MRI.getType(Reg), 128);
7181
case V2S32:
7282
return MRI.getType(Reg) == LLT::fixed_vector(2, 32);
7383
case V4S32:
@@ -110,6 +120,12 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
110120
return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isUniform(Reg);
111121
case UniP8:
112122
return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isUniform(Reg);
123+
case UniPtr32:
124+
return isAnyPtr(MRI.getType(Reg), 32) && MUI.isUniform(Reg);
125+
case UniPtr64:
126+
return isAnyPtr(MRI.getType(Reg), 64) && MUI.isUniform(Reg);
127+
case UniPtr128:
128+
return isAnyPtr(MRI.getType(Reg), 128) && MUI.isUniform(Reg);
113129
case UniV2S16:
114130
return MRI.getType(Reg) == LLT::fixed_vector(2, 16) && MUI.isUniform(Reg);
115131
case UniB32:
@@ -150,6 +166,12 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
150166
return MRI.getType(Reg) == LLT::pointer(6, 32) && MUI.isDivergent(Reg);
151167
case DivP8:
152168
return MRI.getType(Reg) == LLT::pointer(8, 128) && MUI.isDivergent(Reg);
169+
case DivPtr32:
170+
return isAnyPtr(MRI.getType(Reg), 32) && MUI.isDivergent(Reg);
171+
case DivPtr64:
172+
return isAnyPtr(MRI.getType(Reg), 64) && MUI.isDivergent(Reg);
173+
case DivPtr128:
174+
return isAnyPtr(MRI.getType(Reg), 128) && MUI.isDivergent(Reg);
153175
case DivV2S16:
154176
return MRI.getType(Reg) == LLT::fixed_vector(2, 16) && MUI.isDivergent(Reg);
155177
case DivB32:
@@ -223,15 +245,14 @@ UniformityLLTOpPredicateID LLTToId(LLT Ty) {
223245

224246
UniformityLLTOpPredicateID LLTToBId(LLT Ty) {
225247
if (Ty == LLT::scalar(32) || Ty == LLT::fixed_vector(2, 16) ||
226-
(Ty.isPointer() && Ty.getSizeInBits() == 32))
248+
isAnyPtr(Ty, 32))
227249
return B32;
228250
if (Ty == LLT::scalar(64) || Ty == LLT::fixed_vector(2, 32) ||
229-
Ty == LLT::fixed_vector(4, 16) ||
230-
(Ty.isPointer() && Ty.getSizeInBits() == 64))
251+
Ty == LLT::fixed_vector(4, 16) || isAnyPtr(Ty, 64))
231252
return B64;
232253
if (Ty == LLT::fixed_vector(3, 32))
233254
return B96;
234-
if (Ty == LLT::fixed_vector(4, 32))
255+
if (Ty == LLT::fixed_vector(4, 32) || isAnyPtr(Ty, 128))
235256
return B128;
236257
return _;
237258
}

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515

1616
namespace llvm {
1717

18+
class LLT;
1819
class MachineRegisterInfo;
1920
class MachineInstr;
2021
class GCNSubtarget;
@@ -26,6 +27,9 @@ using MachineUniformityInfo = GenericUniformityInfo<MachineSSAContext>;
2627

2728
namespace AMDGPU {
2829

30+
/// \returns true if \p Ty is a pointer type with size \p Width.
31+
bool isAnyPtr(LLT Ty, unsigned Width);
32+
2933
// IDs used to build predicate for RegBankLegalizeRule. Predicate can have one
3034
// or more IDs and each represents a check for 'uniform or divergent' + LLT or
3135
// just LLT on register operand.
@@ -62,6 +66,9 @@ enum UniformityLLTOpPredicateID {
6266
P5,
6367
P6,
6468
P8,
69+
Ptr32,
70+
Ptr64,
71+
Ptr128,
6572

6673
UniP0,
6774
UniP1,
@@ -71,6 +78,9 @@ enum UniformityLLTOpPredicateID {
7178
UniP5,
7279
UniP6,
7380
UniP8,
81+
UniPtr32,
82+
UniPtr64,
83+
UniPtr128,
7484

7585
DivP0,
7686
DivP1,
@@ -80,6 +90,9 @@ enum UniformityLLTOpPredicateID {
8090
DivP5,
8191
DivP6,
8292
DivP8,
93+
DivPtr32,
94+
DivPtr64,
95+
DivPtr128,
8396

8497
// vectors
8598
V2S16,
@@ -138,6 +151,9 @@ enum RegBankLLTMappingApplyID {
138151
SgprP5,
139152
SgprP6,
140153
SgprP8,
154+
SgprPtr32,
155+
SgprPtr64,
156+
SgprPtr128,
141157
SgprV2S16,
142158
SgprV4S32,
143159
SgprV2S32,
@@ -161,6 +177,9 @@ enum RegBankLLTMappingApplyID {
161177
VgprP5,
162178
VgprP6,
163179
VgprP8,
180+
VgprPtr32,
181+
VgprPtr64,
182+
VgprPtr128,
164183
VgprV2S16,
165184
VgprV2S32,
166185
VgprB32,

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