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Add new MMO target flag amdgpu-last-use
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8 files changed

+53
-41
lines changed

8 files changed

+53
-41
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -115,10 +115,8 @@ bool AMDGPUMarkLastScratchLoad::runOnMachineFunction(MachineFunction &MF) {
115115
}
116116

117117
if (LastLoad) {
118-
MachineOperand *LastUse =
119-
SII->getNamedOperand(*LastLoad, AMDGPU::OpName::last_use);
120-
assert(LastUse && "This instruction must have a last_use operand");
121-
LastUse->setImm(1);
118+
MachineMemOperand *MMO = *LastLoad->memoperands_begin();
119+
MMO->setFlags(MOLastUse);
122120
Changed = true;
123121
LLVM_DEBUG(dbgs() << " Found last load: " << *LastLoad;);
124122
}

‎llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ static void buildPrologSpill(const GCNSubtarget &ST, const SIRegisterInfo &TRI,
148148
LiveUnits.addReg(SpillReg);
149149
bool IsKill = !MBB.isLiveIn(SpillReg);
150150
TRI.buildSpillLoadStore(MBB, I, DL, Opc, FI, SpillReg, IsKill, FrameReg,
151-
DwordOff, false, MMO, nullptr, &LiveUnits);
151+
DwordOff, MMO, nullptr, &LiveUnits);
152152
if (IsKill)
153153
LiveUnits.removeReg(SpillReg);
154154
}
@@ -170,7 +170,7 @@ static void buildEpilogRestore(const GCNSubtarget &ST,
170170
PtrInfo, MachineMemOperand::MOLoad, FrameInfo.getObjectSize(FI),
171171
FrameInfo.getObjectAlign(FI));
172172
TRI.buildSpillLoadStore(MBB, I, DL, Opc, FI, SpillReg, false, FrameReg,
173-
DwordOff, false, MMO, nullptr, &LiveUnits);
173+
DwordOff, MMO, nullptr, &LiveUnits);
174174
}
175175

176176
static void buildGitPtr(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8758,6 +8758,7 @@ SIInstrInfo::getSerializableMachineMemOperandTargetFlags() const {
87588758
static const std::pair<MachineMemOperand::Flags, const char *> TargetFlags[] =
87598759
{
87608760
{MONoClobber, "amdgpu-noclobber"},
8761+
{MOLastUse, "amdgpu-last-use"},
87618762
};
87628763

87638764
return ArrayRef(TargetFlags);

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,10 @@ class ScheduleHazardRecognizer;
4141
static const MachineMemOperand::Flags MONoClobber =
4242
MachineMemOperand::MOTargetFlag1;
4343

44+
/// Mark the MMO of a load as the last use.
45+
static const MachineMemOperand::Flags MOLastUse =
46+
MachineMemOperand::MOTargetFlag2;
47+
4448
/// Utility to store machine instructions worklist.
4549
struct SIInstrWorklist {
4650
SIInstrWorklist() = default;

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 14 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1320,8 +1320,8 @@ static unsigned getFlatScratchSpillOpcode(const SIInstrInfo *TII,
13201320
void SIRegisterInfo::buildSpillLoadStore(
13211321
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL,
13221322
unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill,
1323-
MCRegister ScratchOffsetReg, int64_t InstOffset, bool LastUse,
1324-
MachineMemOperand *MMO, RegScavenger *RS, LiveRegUnits *LiveUnits) const {
1323+
MCRegister ScratchOffsetReg, int64_t InstOffset, MachineMemOperand *MMO,
1324+
RegScavenger *RS, LiveRegUnits *LiveUnits) const {
13251325
assert((!RS || !LiveUnits) && "Only RS or LiveUnits can be set but not both");
13261326

13271327
MachineFunction *MF = MBB.getParent();
@@ -1658,10 +1658,11 @@ void SIRegisterInfo::buildSpillLoadStore(
16581658
MIB.addReg(SOffset, SOffsetRegState);
16591659
}
16601660

1661-
assert((!LastUse || AMDGPU::isGFX12Plus(ST)) &&
1662-
"last_use operand exists only on GFX12+");
1663-
int64_t CPol = LastUse ? AMDGPU::CPol::TH_LU : 0;
1664-
MIB.addImm(Offset + RegOffset).addImm(CPol);
1661+
MIB.addImm(Offset + RegOffset);
1662+
1663+
bool LastUse = MMO->getFlags() & MOLastUse;
1664+
MIB.addImm(LastUse ? AMDGPU::CPol::TH_LU : 0); // cpol
1665+
16651666
if (!IsFlat)
16661667
MIB.addImm(0); // swz
16671668
MIB.addMemOperand(NewMMO);
@@ -1737,12 +1738,12 @@ void SIRegisterInfo::buildVGPRSpillLoadStore(SGPRSpillBuilder &SB, int Index,
17371738
unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR
17381739
: AMDGPU::BUFFER_LOAD_DWORD_OFFSET;
17391740
buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, false,
1740-
FrameReg, Offset * SB.EltSize, false, MMO, SB.RS);
1741+
FrameReg, Offset * SB.EltSize, MMO, SB.RS);
17411742
} else {
17421743
unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
17431744
: AMDGPU::BUFFER_STORE_DWORD_OFFSET;
17441745
buildSpillLoadStore(*SB.MBB, SB.MI, SB.DL, Opc, Index, SB.TmpVGPR, IsKill,
1745-
FrameReg, Offset * SB.EltSize, false, MMO, SB.RS);
1746+
FrameReg, Offset * SB.EltSize, MMO, SB.RS);
17461747
// This only ever adds one VGPR spill
17471748
SB.MFI.addToSpilledVGPRs(1);
17481749
}
@@ -2178,7 +2179,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
21782179
}
21792180
buildSpillLoadStore(
21802181
*MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
2181-
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), false,
2182+
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
21822183
*MI->memoperands_begin(), RS);
21832184
MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
21842185
if (IsWWMRegSpill)
@@ -2244,19 +2245,15 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
22442245
TII->insertScratchExecCopy(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy(),
22452246
RS->isRegUsed(AMDGPU::SCC));
22462247
}
2247-
int16_t LastUseIdx =
2248-
AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::last_use);
2249-
bool LastUse =
2250-
LastUseIdx != -1 && MI->getOperand(LastUseIdx).getImm() == 1;
22512248

22522249
buildSpillLoadStore(
22532250
*MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
2254-
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), LastUse,
2251+
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(),
22552252
*MI->memoperands_begin(), RS);
2256-
2257-
if (IsWWMRegSpill)
2253+
2254+
if (IsWWMRegSpill)
22582255
TII->restoreExec(*MF, *MBB, MI, DL, MFI->getSGPRForEXECCopy());
2259-
2256+
22602257
MI->eraseFromParent();
22612258
return true;
22622259
}

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -427,8 +427,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
427427
MachineBasicBlock::iterator MI, const DebugLoc &DL,
428428
unsigned LoadStoreOp, int Index, Register ValueReg,
429429
bool ValueIsKill, MCRegister ScratchOffsetReg,
430-
int64_t InstrOffset, bool LastUse,
431-
MachineMemOperand *MMO, RegScavenger *RS,
430+
int64_t InstrOffset, MachineMemOperand *MMO,
431+
RegScavenger *RS,
432432
LiveRegUnits *LiveUnits = nullptr) const;
433433

434434
// Return alignment in register file of first register in a register tuple.

‎llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -35,18 +35,18 @@ body: |
3535
; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr10, %stack.10, $sp_reg, 0, implicit $exec :: (store (s32) into %stack.10, addrspace 5)
3636
; CHECK-NEXT: SI_SPILL_V32_SAVE $vgpr11, %stack.11, $sp_reg, 0, implicit $exec :: (store (s32) into %stack.11, addrspace 5)
3737
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
38-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.0, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.0, addrspace 5)
39-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE1:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.1, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.1, addrspace 5)
40-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE2:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.2, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.2, addrspace 5)
41-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE3:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.3, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.3, addrspace 5)
42-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE4:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.4, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.4, addrspace 5)
43-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE5:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.5, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.5, addrspace 5)
44-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE6:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.6, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.6, addrspace 5)
45-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE7:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.7, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.7, addrspace 5)
46-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE8:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.8, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.8, addrspace 5)
47-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE9:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.9, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.9, addrspace 5)
48-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE10:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.10, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.10, addrspace 5)
49-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE11:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.11, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.11, addrspace 5)
38+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.0, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.0, addrspace 5)
39+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE1:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.1, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.1, addrspace 5)
40+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE2:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.2, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.2, addrspace 5)
41+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE3:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.3, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.3, addrspace 5)
42+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE4:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.4, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.4, addrspace 5)
43+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE5:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.5, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.5, addrspace 5)
44+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE6:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.6, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.6, addrspace 5)
45+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE7:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.7, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.7, addrspace 5)
46+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE8:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.8, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.8, addrspace 5)
47+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE9:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.9, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.9, addrspace 5)
48+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE10:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.10, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.10, addrspace 5)
49+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE11:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.11, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.11, addrspace 5)
5050
; CHECK-NEXT: S_ENDPGM 0, implicit [[SI_SPILL_V32_RESTORE]], implicit [[SI_SPILL_V32_RESTORE1]], implicit [[SI_SPILL_V32_RESTORE2]], implicit [[SI_SPILL_V32_RESTORE3]], implicit [[SI_SPILL_V32_RESTORE4]], implicit [[SI_SPILL_V32_RESTORE5]], implicit [[SI_SPILL_V32_RESTORE6]], implicit [[SI_SPILL_V32_RESTORE7]], implicit [[SI_SPILL_V32_RESTORE8]], implicit [[SI_SPILL_V32_RESTORE9]], implicit [[SI_SPILL_V32_RESTORE10]], implicit [[SI_SPILL_V32_RESTORE11]]
5151
%0:vgpr_32 = COPY $vgpr0
5252
%1:vgpr_32 = COPY $vgpr1
@@ -76,7 +76,7 @@ body: |
7676
; CHECK-NEXT: {{ $}}
7777
; CHECK-NEXT: SI_SPILL_V384_SAVE $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11, %stack.0, $sp_reg, 0, implicit $exec :: (store (s384) into %stack.0, align 4, addrspace 5)
7878
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
79-
; CHECK-NEXT: [[SI_SPILL_V384_RESTORE:%[0-9]+]]:vreg_384 = SI_SPILL_V384_RESTORE %stack.0, $sp_reg, 0, 1, implicit $exec :: (load (s384) from %stack.0, align 4, addrspace 5)
79+
; CHECK-NEXT: [[SI_SPILL_V384_RESTORE:%[0-9]+]]:vreg_384 = SI_SPILL_V384_RESTORE %stack.0, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s384) from %stack.0, align 4, addrspace 5)
8080
; CHECK-NEXT: S_ENDPGM 0, implicit [[SI_SPILL_V384_RESTORE]]
8181
%0:vreg_384 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
8282
INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11
@@ -157,7 +157,7 @@ body: |
157157
; CHECK-NEXT: SI_SPILL_V32_SAVE [[V_MOV_B32_e32_1]], %stack.14, $sp_reg, 0, implicit $exec :: (store (s32) into %stack.14, addrspace 5)
158158
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE1:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.11, $sp_reg, 0, 0, implicit $exec :: (load (s32) from %stack.11, addrspace 5)
159159
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[V_MOV_B32_e32_]], 0, [[SI_SPILL_V32_RESTORE1]], 0, 0, implicit $mode, implicit $exec
160-
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.14, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.14, addrspace 5)
160+
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.14, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.14, addrspace 5)
161161
; CHECK-NEXT: SI_SPILL_V32_SAVE [[V_MOV_B32_e32_]], %stack.13, $sp_reg, 0, implicit $exec :: (store (s32) into %stack.13, addrspace 5)
162162
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE2:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.10, $sp_reg, 0, 0, implicit $exec :: (load (s32) from %stack.10, addrspace 5)
163163
; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[V_MOV_B32_e32_1]], 0, [[SI_SPILL_V32_RESTORE2]], 0, 0, implicit $mode, implicit $exec
@@ -200,7 +200,7 @@ body: |
200200
; CHECK-NEXT: S_BRANCH %bb.2
201201
; CHECK-NEXT: {{ $}}
202202
; CHECK-NEXT: bb.5:
203-
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE14:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.16, $sp_reg, 0, 1, implicit $exec :: (load (s32) from %stack.16, addrspace 5)
203+
; CHECK-NEXT: [[SI_SPILL_V32_RESTORE14:%[0-9]+]]:vgpr_32 = SI_SPILL_V32_RESTORE %stack.16, $sp_reg, 0, 0, implicit $exec :: ("amdgpu-last-use" load (s32) from %stack.16, addrspace 5)
204204
; CHECK-NEXT: EXP_DONE 0, [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], [[SI_SPILL_V32_RESTORE14]], -1, 0, 15, implicit $exec
205205
; CHECK-NEXT: EXP_DONE 0, %res5, %res6, %res7, %res8, -1, 0, 15, implicit $exec
206206
; CHECK-NEXT: EXP_DONE 0, %res9, %res10, %res11, %res12, -1, 0, 15, implicit $exec

‎llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# RUN: llc -mtriple=amdgcn -run-pass none -o - %s | FileCheck %s
33

44
---
5-
name: target_memoperands
5+
name: target_memoperands_noclobber
66
body: |
77
bb.0:
88
liveins: $sgpr0_sgpr1
@@ -12,3 +12,15 @@ body: |
1212
%0:_(p4) = COPY $sgpr0_sgpr1
1313
%1:_(s32) = G_LOAD %0 :: ("amdgpu-noclobber" load (s32))
1414
...
15+
16+
---
17+
name: target_memoperands_last_use
18+
body: |
19+
bb.0:
20+
liveins: $sgpr0_sgpr1
21+
; CHECK-LABEL: name: target_memoperands
22+
; CHECK: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
23+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p4) :: ("amdgpu-last-use" load (s32))
24+
%0:_(p4) = COPY $sgpr0_sgpr1
25+
%1:_(s32) = G_LOAD %0 :: ("amdgpu-last-use" load (s32))
26+
...

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