Skip to content

Commit b5f2bc2

Browse files
author
Thorsten Schütt
committed
[GlobalIsel][x86] Legalize G_AND, G_OR, and G_XOR for AVX2
check plan: ninja check-llvm-codegen-x86 Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D150658
1 parent 61223c4 commit b5f2bc2

File tree

2 files changed

+152
-0
lines changed

2 files changed

+152
-0
lines changed

‎llvm/lib/Target/X86/X86LegalizerInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -465,6 +465,9 @@ void X86LegalizerInfo::setLegalizerInfoAVX2() {
465465
LegacyLegalizeActions::Legal);
466466
LegacyInfo.setAction({G_UNMERGE_VALUES, Ty}, LegacyLegalizeActions::Legal);
467467
}
468+
469+
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
470+
.legalFor({v8s32, v4s64});
468471
}
469472

470473
void X86LegalizerInfo::setLegalizerInfoAVX512() {

‎llvm/test/CodeGen/X86/GlobalISel/legalize-and-or-xor.mir

Lines changed: 149 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,149 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
2+
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
# test vpand
5+
6+
---
7+
name: test_and_v8s32
8+
alignment: 16
9+
legalized: false
10+
regBankSelected: false
11+
registers:
12+
- { id: 0, class: _, preferred-register: '' }
13+
- { id: 1, class: _, preferred-register: '' }
14+
- { id: 2, class: _, preferred-register: '' }
15+
body: |
16+
bb.1:
17+
18+
; CHECK-LABEL: name: test_and_v8s32
19+
; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
20+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[DEF]], [[DEF]]
21+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[AND]](<8 x s32>)
22+
; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
23+
%0:_(<8 x s32>) = IMPLICIT_DEF
24+
%1:_(<8 x s32>) = G_AND %0, %0
25+
%2:_(<8 x s32>) = COPY %1(<8 x s32>)
26+
RET 0, implicit %2
27+
...
28+
---
29+
name: test_and_v4s64
30+
alignment: 16
31+
legalized: false
32+
regBankSelected: false
33+
registers:
34+
- { id: 0, class: _, preferred-register: '' }
35+
- { id: 1, class: _, preferred-register: '' }
36+
- { id: 2, class: _, preferred-register: '' }
37+
body: |
38+
bb.1:
39+
40+
; CHECK-LABEL: name: test_and_v4s64
41+
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
42+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[DEF]], [[DEF]]
43+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[AND]](<4 x s64>)
44+
; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
45+
%0:_(<4 x s64>) = IMPLICIT_DEF
46+
%1:_(<4 x s64>) = G_AND %0, %0
47+
%2:_(<4 x s64>) = COPY %1(<4 x s64>)
48+
RET 0, implicit %2
49+
...
50+
---
51+
name: test_xor_v4s64
52+
alignment: 16
53+
legalized: false
54+
regBankSelected: false
55+
registers:
56+
- { id: 0, class: _, preferred-register: '' }
57+
- { id: 1, class: _, preferred-register: '' }
58+
liveins:
59+
fixedStack:
60+
stack:
61+
constants:
62+
body: |
63+
bb.1:
64+
; CHECK-LABEL: name: test_xor_v4s64
65+
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
66+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[DEF]], [[DEF]]
67+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[XOR]](<4 x s64>)
68+
; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
69+
%0:_(<4 x s64>) = IMPLICIT_DEF
70+
%1:_(<4 x s64>) = G_XOR %0, %0
71+
%2:_(<4 x s64>) = COPY %1(<4 x s64>)
72+
RET 0, implicit %2
73+
74+
...
75+
---
76+
name: test_xor_v8s32
77+
alignment: 16
78+
legalized: false
79+
regBankSelected: false
80+
registers:
81+
- { id: 0, class: _, preferred-register: '' }
82+
- { id: 1, class: _, preferred-register: '' }
83+
liveins:
84+
fixedStack:
85+
stack:
86+
constants:
87+
body: |
88+
bb.1:
89+
; CHECK-LABEL: name: test_xor_v8s32
90+
; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
91+
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[DEF]], [[DEF]]
92+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[XOR]](<8 x s32>)
93+
; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
94+
%0:_(<8 x s32>) = IMPLICIT_DEF
95+
%1:_(<8 x s32>) = G_XOR %0, %0
96+
%2:_(<8 x s32>) = COPY %1(<8 x s32>)
97+
RET 0, implicit %2
98+
99+
...
100+
---
101+
name: test_or_v4s64
102+
alignment: 16
103+
legalized: false
104+
regBankSelected: false
105+
registers:
106+
- { id: 0, class: _, preferred-register: '' }
107+
- { id: 1, class: _, preferred-register: '' }
108+
liveins:
109+
fixedStack:
110+
stack:
111+
constants:
112+
body: |
113+
bb.1:
114+
; CHECK-LABEL: name: test_or_v4s64
115+
; CHECK: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
116+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[DEF]], [[DEF]]
117+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY [[OR]](<4 x s64>)
118+
; CHECK-NEXT: RET 0, implicit [[COPY]](<4 x s64>)
119+
%0:_(<4x s64>) = IMPLICIT_DEF
120+
%1:_(<4x s64>) = G_OR %0, %0
121+
%2:_(<4x s64>) = COPY %1(<4x s64>)
122+
RET 0, implicit %2
123+
124+
...
125+
---
126+
name: test_or_v8s32
127+
alignment: 16
128+
legalized: false
129+
regBankSelected: false
130+
registers:
131+
- { id: 0, class: _, preferred-register: '' }
132+
- { id: 1, class: _, preferred-register: '' }
133+
liveins:
134+
fixedStack:
135+
stack:
136+
constants:
137+
body: |
138+
bb.1:
139+
; CHECK-LABEL: name: test_or_v8s32
140+
; CHECK: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
141+
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[DEF]], [[DEF]]
142+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY [[OR]](<8 x s32>)
143+
; CHECK-NEXT: RET 0, implicit [[COPY]](<8 x s32>)
144+
%0:_(<8x s32>) = IMPLICIT_DEF
145+
%1:_(<8x s32>) = G_OR %0, %0
146+
%2:_(<8x s32>) = COPY %1(<8x s32>)
147+
RET 0, implicit %2
148+
149+
...

0 commit comments

Comments
 (0)