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[RISCV] Generalize (srl (and X, 0xffff), C) -> (srli (slli X, (XLen-16), (XLen-16) + C) optimization.
This can be generalized to (srl (and X, C2), C) -> (srli (slli X, (XLen-C3), (XLen-C3) + C). Where C2 is a mask with C3 trailing ones. This can avoid constant materialization for C2. This is beneficial even when C2 can be selected to ANDI because the SLLI can become C.SLLI, but C.ANDI cannot cover all the immediates of ANDI. This also enables CSE in some cases of i8 sdiv by constant codegen.
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-178
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10 files changed

+142
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‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 32 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -542,35 +542,38 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
542542
return;
543543
}
544544
case ISD::SRL: {
545-
// Optimize (srl (and X, 0xffff), C) ->
546-
// (srli (slli X, (XLen-16), (XLen-16) + C)
547-
// Taking into account that the 0xffff may have had lower bits unset by
548-
// SimplifyDemandedBits. This avoids materializing the 0xffff immediate.
549-
// This pattern occurs when type legalizing i16 right shifts.
550-
// FIXME: This could be extended to other AND masks.
545+
// Optimize (srl (and X, C2), C) ->
546+
// (srli (slli X, (XLen-C3), (XLen-C3) + C)
547+
// Where C2 is a mask with C3 trailing ones.
548+
// Taking into account that the C2 may have had lower bits unset by
549+
// SimplifyDemandedBits. This avoids materializing the C2 immediate.
550+
// This pattern occurs when type legalizing right shifts for types with
551+
// less than XLen bits.
551552
auto *N1C = dyn_cast<ConstantSDNode>(Node->getOperand(1));
552-
if (N1C) {
553-
uint64_t ShAmt = N1C->getZExtValue();
554-
SDValue N0 = Node->getOperand(0);
555-
if (ShAmt < 16 && N0.getOpcode() == ISD::AND && N0.hasOneUse() &&
556-
isa<ConstantSDNode>(N0.getOperand(1))) {
557-
uint64_t Mask = N0.getConstantOperandVal(1);
558-
Mask |= maskTrailingOnes<uint64_t>(ShAmt);
559-
if (Mask == 0xffff) {
560-
unsigned LShAmt = Subtarget->getXLen() - 16;
561-
SDNode *SLLI =
562-
CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
563-
CurDAG->getTargetConstant(LShAmt, DL, VT));
564-
SDNode *SRLI = CurDAG->getMachineNode(
565-
RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
566-
CurDAG->getTargetConstant(LShAmt + ShAmt, DL, VT));
567-
ReplaceNode(Node, SRLI);
568-
return;
569-
}
570-
}
571-
}
572-
573-
break;
553+
if (!N1C)
554+
break;
555+
SDValue N0 = Node->getOperand(0);
556+
if (N0.getOpcode() != ISD::AND || !N0.hasOneUse() ||
557+
!isa<ConstantSDNode>(N0.getOperand(1)))
558+
break;
559+
unsigned ShAmt = N1C->getZExtValue();
560+
uint64_t Mask = N0.getConstantOperandVal(1);
561+
Mask |= maskTrailingOnes<uint64_t>(ShAmt);
562+
if (!isMask_64(Mask))
563+
break;
564+
unsigned TrailingOnes = countTrailingOnes(Mask);
565+
// 32 trailing ones should use srliw via tablegen pattern.
566+
if (TrailingOnes == 32 || ShAmt >= TrailingOnes)
567+
break;
568+
unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
569+
SDNode *SLLI =
570+
CurDAG->getMachineNode(RISCV::SLLI, DL, VT, N0->getOperand(0),
571+
CurDAG->getTargetConstant(LShAmt, DL, VT));
572+
SDNode *SRLI = CurDAG->getMachineNode(
573+
RISCV::SRLI, DL, VT, SDValue(SLLI, 0),
574+
CurDAG->getTargetConstant(LShAmt + ShAmt, DL, VT));
575+
ReplaceNode(Node, SRLI);
576+
return;
574577
}
575578
case ISD::SRA: {
576579
// Optimize (sra (sext_inreg X, i16), C) ->
@@ -587,7 +590,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
587590
SDValue N0 = Node->getOperand(0);
588591
if (N0.getOpcode() != ISD::SIGN_EXTEND_INREG || !N0.hasOneUse())
589592
break;
590-
uint64_t ShAmt = N1C->getZExtValue();
593+
unsigned ShAmt = N1C->getZExtValue();
591594
unsigned ExtSize =
592595
cast<VTSDNode>(N0.getOperand(1))->getVT().getSizeInBits();
593596
// ExtSize of 32 should use sraiw via tablegen pattern.

‎llvm/test/CodeGen/RISCV/alu8.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -135,14 +135,14 @@ define i8 @slli(i8 %a) nounwind {
135135
define i8 @srli(i8 %a) nounwind {
136136
; RV32I-LABEL: srli:
137137
; RV32I: # %bb.0:
138-
; RV32I-NEXT: andi a0, a0, 192
139-
; RV32I-NEXT: srli a0, a0, 6
138+
; RV32I-NEXT: slli a0, a0, 24
139+
; RV32I-NEXT: srli a0, a0, 30
140140
; RV32I-NEXT: ret
141141
;
142142
; RV64I-LABEL: srli:
143143
; RV64I: # %bb.0:
144-
; RV64I-NEXT: andi a0, a0, 192
145-
; RV64I-NEXT: srli a0, a0, 6
144+
; RV64I-NEXT: slli a0, a0, 56
145+
; RV64I-NEXT: srli a0, a0, 62
146146
; RV64I-NEXT: ret
147147
%1 = lshr i8 %a, 6
148148
ret i8 %1

‎llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -212,10 +212,8 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
212212
; RV32I-NEXT: and a0, a0, a1
213213
; RV32I-NEXT: slli a1, a0, 8
214214
; RV32I-NEXT: add a0, a1, a0
215-
; RV32I-NEXT: lui a1, 2
216-
; RV32I-NEXT: addi a1, a1, -256
217-
; RV32I-NEXT: and a0, a0, a1
218-
; RV32I-NEXT: srli a0, a0, 8
215+
; RV32I-NEXT: slli a0, a0, 19
216+
; RV32I-NEXT: srli a0, a0, 27
219217
; RV32I-NEXT: ret
220218
; RV32I-NEXT: .LBB4_2:
221219
; RV32I-NEXT: li a0, 16
@@ -247,12 +245,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
247245
; RV64I-NEXT: lui a1, 1
248246
; RV64I-NEXT: addiw a1, a1, -241
249247
; RV64I-NEXT: and a0, a0, a1
250-
; RV64I-NEXT: slli a1, a0, 8
251-
; RV64I-NEXT: add a0, a1, a0
252-
; RV64I-NEXT: lui a1, 2
253-
; RV64I-NEXT: addiw a1, a1, -256
254-
; RV64I-NEXT: and a0, a0, a1
255-
; RV64I-NEXT: srli a0, a0, 8
248+
; RV64I-NEXT: slliw a1, a0, 8
249+
; RV64I-NEXT: addw a0, a1, a0
250+
; RV64I-NEXT: slli a0, a0, 51
251+
; RV64I-NEXT: srli a0, a0, 59
256252
; RV64I-NEXT: ret
257253
; RV64I-NEXT: .LBB4_2:
258254
; RV64I-NEXT: li a0, 16
@@ -605,10 +601,8 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
605601
; RV32I-NEXT: and a0, a0, a1
606602
; RV32I-NEXT: slli a1, a0, 8
607603
; RV32I-NEXT: add a0, a1, a0
608-
; RV32I-NEXT: lui a1, 2
609-
; RV32I-NEXT: addi a1, a1, -256
610-
; RV32I-NEXT: and a0, a0, a1
611-
; RV32I-NEXT: srli a0, a0, 8
604+
; RV32I-NEXT: slli a0, a0, 19
605+
; RV32I-NEXT: srli a0, a0, 27
612606
; RV32I-NEXT: ret
613607
;
614608
; RV64I-LABEL: test_cttz_i16_zero_undef:
@@ -632,12 +626,10 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
632626
; RV64I-NEXT: lui a1, 1
633627
; RV64I-NEXT: addiw a1, a1, -241
634628
; RV64I-NEXT: and a0, a0, a1
635-
; RV64I-NEXT: slli a1, a0, 8
636-
; RV64I-NEXT: add a0, a1, a0
637-
; RV64I-NEXT: lui a1, 2
638-
; RV64I-NEXT: addiw a1, a1, -256
639-
; RV64I-NEXT: and a0, a0, a1
640-
; RV64I-NEXT: srli a0, a0, 8
629+
; RV64I-NEXT: slliw a1, a0, 8
630+
; RV64I-NEXT: addw a0, a1, a0
631+
; RV64I-NEXT: slli a0, a0, 51
632+
; RV64I-NEXT: srli a0, a0, 59
641633
; RV64I-NEXT: ret
642634
%tmp = call i16 @llvm.cttz.i16(i16 %a, i1 true)
643635
ret i16 %tmp

‎llvm/test/CodeGen/RISCV/div-by-constant.ll

Lines changed: 16 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -163,8 +163,8 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
163163
; RV32IM-NEXT: mul a1, a1, a2
164164
; RV32IM-NEXT: srli a1, a1, 8
165165
; RV32IM-NEXT: sub a0, a0, a1
166-
; RV32IM-NEXT: andi a0, a0, 254
167-
; RV32IM-NEXT: srli a0, a0, 1
166+
; RV32IM-NEXT: slli a0, a0, 24
167+
; RV32IM-NEXT: srli a0, a0, 25
168168
; RV32IM-NEXT: add a0, a0, a1
169169
; RV32IM-NEXT: srli a0, a0, 2
170170
; RV32IM-NEXT: ret
@@ -176,8 +176,8 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
176176
; RV32IMZB-NEXT: sh2add a1, a2, a1
177177
; RV32IMZB-NEXT: srli a1, a1, 8
178178
; RV32IMZB-NEXT: sub a0, a0, a1
179-
; RV32IMZB-NEXT: andi a0, a0, 254
180-
; RV32IMZB-NEXT: srli a0, a0, 1
179+
; RV32IMZB-NEXT: slli a0, a0, 24
180+
; RV32IMZB-NEXT: srli a0, a0, 25
181181
; RV32IMZB-NEXT: add a0, a0, a1
182182
; RV32IMZB-NEXT: srli a0, a0, 2
183183
; RV32IMZB-NEXT: ret
@@ -189,8 +189,8 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
189189
; RV64IM-NEXT: mul a1, a1, a2
190190
; RV64IM-NEXT: srli a1, a1, 8
191191
; RV64IM-NEXT: subw a0, a0, a1
192-
; RV64IM-NEXT: andi a0, a0, 254
193-
; RV64IM-NEXT: srli a0, a0, 1
192+
; RV64IM-NEXT: slli a0, a0, 56
193+
; RV64IM-NEXT: srli a0, a0, 57
194194
; RV64IM-NEXT: add a0, a0, a1
195195
; RV64IM-NEXT: srli a0, a0, 2
196196
; RV64IM-NEXT: ret
@@ -202,8 +202,8 @@ define i8 @udiv8_constant_add(i8 %a) nounwind {
202202
; RV64IMZB-NEXT: sh2add a1, a2, a1
203203
; RV64IMZB-NEXT: srli a1, a1, 8
204204
; RV64IMZB-NEXT: subw a0, a0, a1
205-
; RV64IMZB-NEXT: andi a0, a0, 254
206-
; RV64IMZB-NEXT: srli a0, a0, 1
205+
; RV64IMZB-NEXT: slli a0, a0, 56
206+
; RV64IMZB-NEXT: srli a0, a0, 57
207207
; RV64IMZB-NEXT: add a0, a0, a1
208208
; RV64IMZB-NEXT: srli a0, a0, 2
209209
; RV64IMZB-NEXT: ret
@@ -618,8 +618,6 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
618618
ret i8 %1
619619
}
620620

621-
; FIXME: Can shorten the code after the mul by using slli+srai/srli like the
622-
; i16 version without Zbb.
623621
define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
624622
; RV32IM-LABEL: sdiv8_constant_add_srai:
625623
; RV32IM: # %bb.0:
@@ -629,9 +627,8 @@ define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
629627
; RV32IM-NEXT: mul a1, a1, a2
630628
; RV32IM-NEXT: srli a1, a1, 8
631629
; RV32IM-NEXT: add a0, a1, a0
632-
; RV32IM-NEXT: andi a1, a0, 128
633-
; RV32IM-NEXT: srli a1, a1, 7
634630
; RV32IM-NEXT: slli a0, a0, 24
631+
; RV32IM-NEXT: srli a1, a0, 31
635632
; RV32IM-NEXT: srai a0, a0, 26
636633
; RV32IM-NEXT: add a0, a0, a1
637634
; RV32IM-NEXT: ret
@@ -643,9 +640,8 @@ define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
643640
; RV32IMZB-NEXT: mul a1, a1, a2
644641
; RV32IMZB-NEXT: srli a1, a1, 8
645642
; RV32IMZB-NEXT: add a0, a1, a0
646-
; RV32IMZB-NEXT: andi a1, a0, 128
647-
; RV32IMZB-NEXT: srli a1, a1, 7
648643
; RV32IMZB-NEXT: slli a0, a0, 24
644+
; RV32IMZB-NEXT: srli a1, a0, 31
649645
; RV32IMZB-NEXT: srai a0, a0, 26
650646
; RV32IMZB-NEXT: add a0, a0, a1
651647
; RV32IMZB-NEXT: ret
@@ -658,9 +654,8 @@ define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
658654
; RV64IM-NEXT: mul a1, a1, a2
659655
; RV64IM-NEXT: srli a1, a1, 8
660656
; RV64IM-NEXT: addw a0, a1, a0
661-
; RV64IM-NEXT: andi a1, a0, 128
662-
; RV64IM-NEXT: srli a1, a1, 7
663657
; RV64IM-NEXT: slli a0, a0, 56
658+
; RV64IM-NEXT: srli a1, a0, 63
664659
; RV64IM-NEXT: srai a0, a0, 58
665660
; RV64IM-NEXT: add a0, a0, a1
666661
; RV64IM-NEXT: ret
@@ -672,18 +667,15 @@ define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
672667
; RV64IMZB-NEXT: mul a1, a1, a2
673668
; RV64IMZB-NEXT: srli a1, a1, 8
674669
; RV64IMZB-NEXT: addw a0, a1, a0
675-
; RV64IMZB-NEXT: andi a1, a0, 128
676-
; RV64IMZB-NEXT: srli a1, a1, 7
677670
; RV64IMZB-NEXT: slli a0, a0, 56
671+
; RV64IMZB-NEXT: srli a1, a0, 63
678672
; RV64IMZB-NEXT: srai a0, a0, 58
679673
; RV64IMZB-NEXT: add a0, a0, a1
680674
; RV64IMZB-NEXT: ret
681675
%1 = sdiv i8 %a, 7
682676
ret i8 %1
683677
}
684678

685-
; FIXME: Can shorten the code after the mul by using slli+srai/srli like the
686-
; i16 version without Zbb.
687679
define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
688680
; RV32IM-LABEL: sdiv8_constant_sub_srai:
689681
; RV32IM: # %bb.0:
@@ -693,9 +685,8 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
693685
; RV32IM-NEXT: mul a1, a1, a2
694686
; RV32IM-NEXT: srli a1, a1, 8
695687
; RV32IM-NEXT: sub a0, a1, a0
696-
; RV32IM-NEXT: andi a1, a0, 128
697-
; RV32IM-NEXT: srli a1, a1, 7
698688
; RV32IM-NEXT: slli a0, a0, 24
689+
; RV32IM-NEXT: srli a1, a0, 31
699690
; RV32IM-NEXT: srai a0, a0, 26
700691
; RV32IM-NEXT: add a0, a0, a1
701692
; RV32IM-NEXT: ret
@@ -707,9 +698,8 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
707698
; RV32IMZB-NEXT: mul a1, a1, a2
708699
; RV32IMZB-NEXT: srli a1, a1, 8
709700
; RV32IMZB-NEXT: sub a0, a1, a0
710-
; RV32IMZB-NEXT: andi a1, a0, 128
711-
; RV32IMZB-NEXT: srli a1, a1, 7
712701
; RV32IMZB-NEXT: slli a0, a0, 24
702+
; RV32IMZB-NEXT: srli a1, a0, 31
713703
; RV32IMZB-NEXT: srai a0, a0, 26
714704
; RV32IMZB-NEXT: add a0, a0, a1
715705
; RV32IMZB-NEXT: ret
@@ -722,9 +712,8 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
722712
; RV64IM-NEXT: mul a1, a1, a2
723713
; RV64IM-NEXT: srli a1, a1, 8
724714
; RV64IM-NEXT: subw a0, a1, a0
725-
; RV64IM-NEXT: andi a1, a0, 128
726-
; RV64IM-NEXT: srli a1, a1, 7
727715
; RV64IM-NEXT: slli a0, a0, 56
716+
; RV64IM-NEXT: srli a1, a0, 63
728717
; RV64IM-NEXT: srai a0, a0, 58
729718
; RV64IM-NEXT: add a0, a0, a1
730719
; RV64IM-NEXT: ret
@@ -736,9 +725,8 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
736725
; RV64IMZB-NEXT: mul a1, a1, a2
737726
; RV64IMZB-NEXT: srli a1, a1, 8
738727
; RV64IMZB-NEXT: subw a0, a1, a0
739-
; RV64IMZB-NEXT: andi a1, a0, 128
740-
; RV64IMZB-NEXT: srli a1, a1, 7
741728
; RV64IMZB-NEXT: slli a0, a0, 56
729+
; RV64IMZB-NEXT: srli a1, a0, 63
742730
; RV64IMZB-NEXT: srai a0, a0, 58
743731
; RV64IMZB-NEXT: add a0, a0, a1
744732
; RV64IMZB-NEXT: ret

‎llvm/test/CodeGen/RISCV/div.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -363,26 +363,26 @@ define i8 @udiv8_constant(i8 %a) nounwind {
363363
define i8 @udiv8_pow2(i8 %a) nounwind {
364364
; RV32I-LABEL: udiv8_pow2:
365365
; RV32I: # %bb.0:
366-
; RV32I-NEXT: andi a0, a0, 248
367-
; RV32I-NEXT: srli a0, a0, 3
366+
; RV32I-NEXT: slli a0, a0, 24
367+
; RV32I-NEXT: srli a0, a0, 27
368368
; RV32I-NEXT: ret
369369
;
370370
; RV32IM-LABEL: udiv8_pow2:
371371
; RV32IM: # %bb.0:
372-
; RV32IM-NEXT: andi a0, a0, 248
373-
; RV32IM-NEXT: srli a0, a0, 3
372+
; RV32IM-NEXT: slli a0, a0, 24
373+
; RV32IM-NEXT: srli a0, a0, 27
374374
; RV32IM-NEXT: ret
375375
;
376376
; RV64I-LABEL: udiv8_pow2:
377377
; RV64I: # %bb.0:
378-
; RV64I-NEXT: andi a0, a0, 248
379-
; RV64I-NEXT: srli a0, a0, 3
378+
; RV64I-NEXT: slli a0, a0, 56
379+
; RV64I-NEXT: srli a0, a0, 59
380380
; RV64I-NEXT: ret
381381
;
382382
; RV64IM-LABEL: udiv8_pow2:
383383
; RV64IM: # %bb.0:
384-
; RV64IM-NEXT: andi a0, a0, 248
385-
; RV64IM-NEXT: srli a0, a0, 3
384+
; RV64IM-NEXT: slli a0, a0, 56
385+
; RV64IM-NEXT: srli a0, a0, 59
386386
; RV64IM-NEXT: ret
387387
%1 = udiv i8 %a, 8
388388
ret i8 %1

‎llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -473,20 +473,20 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
473473
define i8 @srli_i8(i8 %a) nounwind {
474474
; RV32I-LABEL: srli_i8:
475475
; RV32I: # %bb.0:
476-
; RV32I-NEXT: andi a0, a0, 192
477-
; RV32I-NEXT: srli a0, a0, 6
476+
; RV32I-NEXT: slli a0, a0, 24
477+
; RV32I-NEXT: srli a0, a0, 30
478478
; RV32I-NEXT: ret
479479
;
480480
; RV32ZBB-LABEL: srli_i8:
481481
; RV32ZBB: # %bb.0:
482-
; RV32ZBB-NEXT: andi a0, a0, 192
483-
; RV32ZBB-NEXT: srli a0, a0, 6
482+
; RV32ZBB-NEXT: slli a0, a0, 24
483+
; RV32ZBB-NEXT: srli a0, a0, 30
484484
; RV32ZBB-NEXT: ret
485485
;
486486
; RV32ZBP-LABEL: srli_i8:
487487
; RV32ZBP: # %bb.0:
488-
; RV32ZBP-NEXT: andi a0, a0, 192
489-
; RV32ZBP-NEXT: srli a0, a0, 6
488+
; RV32ZBP-NEXT: slli a0, a0, 24
489+
; RV32ZBP-NEXT: srli a0, a0, 30
490490
; RV32ZBP-NEXT: ret
491491
%1 = lshr i8 %a, 6
492492
ret i8 %1

‎llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -544,20 +544,20 @@ define i64 @rori_i64_fshr(i64 %a) nounwind {
544544
define i8 @srli_i8(i8 %a) nounwind {
545545
; RV64I-LABEL: srli_i8:
546546
; RV64I: # %bb.0:
547-
; RV64I-NEXT: andi a0, a0, 192
548-
; RV64I-NEXT: srli a0, a0, 6
547+
; RV64I-NEXT: slli a0, a0, 56
548+
; RV64I-NEXT: srli a0, a0, 62
549549
; RV64I-NEXT: ret
550550
;
551551
; RV64ZBB-LABEL: srli_i8:
552552
; RV64ZBB: # %bb.0:
553-
; RV64ZBB-NEXT: andi a0, a0, 192
554-
; RV64ZBB-NEXT: srli a0, a0, 6
553+
; RV64ZBB-NEXT: slli a0, a0, 56
554+
; RV64ZBB-NEXT: srli a0, a0, 62
555555
; RV64ZBB-NEXT: ret
556556
;
557557
; RV64ZBP-LABEL: srli_i8:
558558
; RV64ZBP: # %bb.0:
559-
; RV64ZBP-NEXT: andi a0, a0, 192
560-
; RV64ZBP-NEXT: srli a0, a0, 6
559+
; RV64ZBP-NEXT: slli a0, a0, 56
560+
; RV64ZBP-NEXT: srli a0, a0, 62
561561
; RV64ZBP-NEXT: ret
562562
%1 = lshr i8 %a, 6
563563
ret i8 %1

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