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[AArch64] Check for immediates using isLegalICmpImmediate
We can catch negatives that can be encoded in cmn this way!
1 parent eccb7d2 commit b652d2c

14 files changed

+129
-147
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 36 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -3330,6 +3330,14 @@ static bool isLegalArithImmed(uint64_t C) {
33303330
return IsLegal;
33313331
}
33323332

3333+
bool isLegalCmpImmed(APInt C) {
3334+
if (C.isMinSignedValue())
3335+
return false;
3336+
// Works for negative immediates too, as it can be written as an ADDS
3337+
// instruction with a negated immediate.
3338+
return isLegalArithImmed(C.abs().getZExtValue());
3339+
}
3340+
33333341
static bool cannotBeIntMin(SDValue CheckedVal, SelectionDAG &DAG) {
33343342
KnownBits KnownSrc = DAG.computeKnownBits(CheckedVal);
33353343
return !KnownSrc.getSignedMinValue().isMinSignedValue();
@@ -3760,53 +3768,50 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
37603768
const SDLoc &dl) {
37613769
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
37623770
EVT VT = RHS.getValueType();
3763-
uint64_t C = RHSC->getZExtValue();
3764-
if (!isLegalArithImmed(C)) {
3771+
APInt C = RHSC->getAPIntValue();
3772+
if (!isLegalCmpImmed(C)) {
37653773
// Constant does not fit, try adjusting it by one?
37663774
switch (CC) {
37673775
default:
37683776
break;
37693777
case ISD::SETLT:
37703778
case ISD::SETGE:
3771-
if ((VT == MVT::i32 && C != 0x80000000 &&
3772-
isLegalArithImmed((uint32_t)(C - 1))) ||
3773-
(VT == MVT::i64 && C != 0x80000000ULL &&
3774-
isLegalArithImmed(C - 1ULL))) {
3775-
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3776-
C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
3777-
RHS = DAG.getConstant(C, dl, VT);
3779+
if (!C.isMinSignedValue()) {
3780+
APInt CMinusOne = C - 1;
3781+
if (isLegalCmpImmed(CMinusOne)) {
3782+
CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3783+
RHS = DAG.getConstant(CMinusOne, dl, VT);
3784+
}
37783785
}
37793786
break;
37803787
case ISD::SETULT:
37813788
case ISD::SETUGE:
3782-
if ((VT == MVT::i32 && C != 0 &&
3783-
isLegalArithImmed((uint32_t)(C - 1))) ||
3784-
(VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
3785-
CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3786-
C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
3787-
RHS = DAG.getConstant(C, dl, VT);
3789+
if (!C.isZero()) {
3790+
APInt CMinusOne = C - 1;
3791+
if (isLegalCmpImmed(CMinusOne)) {
3792+
CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3793+
RHS = DAG.getConstant(CMinusOne, dl, VT);
3794+
}
37883795
}
37893796
break;
37903797
case ISD::SETLE:
37913798
case ISD::SETGT:
3792-
if ((VT == MVT::i32 && C != INT32_MAX &&
3793-
isLegalArithImmed((uint32_t)(C + 1))) ||
3794-
(VT == MVT::i64 && C != INT64_MAX &&
3795-
isLegalArithImmed(C + 1ULL))) {
3796-
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3797-
C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
3798-
RHS = DAG.getConstant(C, dl, VT);
3799+
if (!C.isMaxSignedValue()) {
3800+
APInt CPlusOne = C + 1;
3801+
if (isLegalCmpImmed(CPlusOne)) {
3802+
CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3803+
RHS = DAG.getConstant(CPlusOne, dl, VT);
3804+
}
37993805
}
38003806
break;
38013807
case ISD::SETULE:
38023808
case ISD::SETUGT:
3803-
if ((VT == MVT::i32 && C != UINT32_MAX &&
3804-
isLegalArithImmed((uint32_t)(C + 1))) ||
3805-
(VT == MVT::i64 && C != UINT64_MAX &&
3806-
isLegalArithImmed(C + 1ULL))) {
3807-
CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3808-
C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
3809-
RHS = DAG.getConstant(C, dl, VT);
3809+
if (!C.isAllOnes()) {
3810+
APInt CPlusOne = C + 1;
3811+
if (isLegalCmpImmed(CPlusOne)) {
3812+
CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3813+
RHS = DAG.getConstant(CPlusOne, dl, VT);
3814+
}
38103815
}
38113816
break;
38123817
}
@@ -3823,8 +3828,7 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
38233828
// cmp w13, w12
38243829
// can be turned into:
38253830
// cmp w12, w11, lsl #1
3826-
if (!isa<ConstantSDNode>(RHS) ||
3827-
!isLegalArithImmed(RHS->getAsAPIntVal().abs().getZExtValue())) {
3831+
if (!isa<ConstantSDNode>(RHS) || !isLegalCmpImmed(RHS->getAsAPIntVal())) {
38283832
bool LHSIsCMN = isCMN(LHS, CC, DAG);
38293833
bool RHSIsCMN = isCMN(RHS, CC, DAG);
38303834
SDValue TheLHS = LHSIsCMN ? LHS.getOperand(1) : LHS;
@@ -17353,17 +17357,10 @@ LLT AArch64TargetLowering::getOptimalMemOpLLT(
1735317357
// 12-bit optionally shifted immediates are legal for adds.
1735417358
bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
1735517359
if (Immed == std::numeric_limits<int64_t>::min()) {
17356-
LLVM_DEBUG(dbgs() << "Illegal add imm " << Immed
17357-
<< ": avoid UB for INT64_MIN\n");
1735817360
return false;
1735917361
}
1736017362
// Same encoding for add/sub, just flip the sign.
17361-
Immed = std::abs(Immed);
17362-
bool IsLegal = ((Immed >> 12) == 0 ||
17363-
((Immed & 0xfff) == 0 && Immed >> 24 == 0));
17364-
LLVM_DEBUG(dbgs() << "Is " << Immed
17365-
<< " legal add imm: " << (IsLegal ? "yes" : "no") << "\n");
17366-
return IsLegal;
17363+
return isLegalArithImmed((uint64_t)std::abs(Immed));
1736717364
}
1736817365

1736917366
bool AArch64TargetLowering::isLegalAddScalableImmediate(int64_t Imm) const {

‎llvm/test/CodeGen/AArch64/arm64-csel.ll

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -100,9 +100,8 @@ define i32 @foo7(i32 %a, i32 %b) nounwind {
100100
; CHECK-NEXT: subs w8, w0, w1
101101
; CHECK-NEXT: cneg w9, w8, mi
102102
; CHECK-NEXT: cmn w8, #1
103-
; CHECK-NEXT: csel w10, w9, w0, lt
104-
; CHECK-NEXT: cmp w8, #0
105-
; CHECK-NEXT: csel w0, w10, w9, ge
103+
; CHECK-NEXT: csel w8, w9, w0, lt
104+
; CHECK-NEXT: csel w0, w8, w9, gt
106105
; CHECK-NEXT: ret
107106
entry:
108107
%sub = sub nsw i32 %a, %b

‎llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,8 @@ define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
1414
; CHECK-LABEL: f_i8_sign_extend_inreg:
1515
; CHECK: // %bb.0: // %entry
1616
; CHECK-NEXT: sxtb w8, w0
17-
; CHECK-NEXT: cmp w8, #0
18-
; CHECK-NEXT: csel w8, w1, w2, ge
17+
; CHECK-NEXT: cmn w8, #1
18+
; CHECK-NEXT: csel w8, w1, w2, gt
1919
; CHECK-NEXT: add w0, w8, w0, uxtb
2020
; CHECK-NEXT: ret
2121
entry:
@@ -36,8 +36,8 @@ define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
3636
; CHECK-LABEL: f_i16_sign_extend_inreg:
3737
; CHECK: // %bb.0: // %entry
3838
; CHECK-NEXT: sxth w8, w0
39-
; CHECK-NEXT: cmp w8, #0
40-
; CHECK-NEXT: csel w8, w1, w2, ge
39+
; CHECK-NEXT: cmn w8, #1
40+
; CHECK-NEXT: csel w8, w1, w2, gt
4141
; CHECK-NEXT: add w0, w8, w0, uxth
4242
; CHECK-NEXT: ret
4343
entry:
@@ -57,8 +57,8 @@ B:
5757
define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
5858
; CHECK-LABEL: f_i32_sign_extend_inreg:
5959
; CHECK: // %bb.0: // %entry
60-
; CHECK-NEXT: cmp w0, #0
61-
; CHECK-NEXT: csel x8, x1, x2, ge
60+
; CHECK-NEXT: cmn w0, #1
61+
; CHECK-NEXT: csel x8, x1, x2, gt
6262
; CHECK-NEXT: add x0, x8, w0, uxtw
6363
; CHECK-NEXT: ret
6464
entry:
@@ -145,8 +145,8 @@ define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
145145
; CHECK: // %bb.0: // %entry
146146
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
147147
; CHECK-NEXT: sxtw x8, w0
148-
; CHECK-NEXT: cmp x8, #0
149-
; CHECK-NEXT: csel x8, x1, x2, ge
148+
; CHECK-NEXT: cmn x8, #1
149+
; CHECK-NEXT: csel x8, x1, x2, gt
150150
; CHECK-NEXT: add x0, x8, w0, uxtw
151151
; CHECK-NEXT: ret
152152
entry:

‎llvm/test/CodeGen/AArch64/cmp-to-cmn.ll

Lines changed: 16 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -446,10 +446,8 @@ define i1 @cmn_large_imm(i32 %a) {
446446
define i1 @almost_immediate_neg_slt(i32 %x) {
447447
; CHECK-LABEL: almost_immediate_neg_slt:
448448
; CHECK: // %bb.0:
449-
; CHECK-NEXT: mov w8, #4097 // =0x1001
450-
; CHECK-NEXT: movk w8, #65281, lsl #16
451-
; CHECK-NEXT: cmp w0, w8
452-
; CHECK-NEXT: cset w0, lt
449+
; CHECK-NEXT: cmn w0, #4079, lsl #12 // =16707584
450+
; CHECK-NEXT: cset w0, le
453451
; CHECK-NEXT: ret
454452
%cmp = icmp slt i32 %x, -16707583
455453
ret i1 %cmp
@@ -458,10 +456,8 @@ define i1 @almost_immediate_neg_slt(i32 %x) {
458456
define i1 @almost_immediate_neg_slt_64(i64 %x) {
459457
; CHECK-LABEL: almost_immediate_neg_slt_64:
460458
; CHECK: // %bb.0:
461-
; CHECK-NEXT: mov x8, #-61439 // =0xffffffffffff1001
462-
; CHECK-NEXT: movk x8, #65281, lsl #16
463-
; CHECK-NEXT: cmp x0, x8
464-
; CHECK-NEXT: cset w0, lt
459+
; CHECK-NEXT: cmn x0, #4079, lsl #12 // =16707584
460+
; CHECK-NEXT: cset w0, le
465461
; CHECK-NEXT: ret
466462
%cmp = icmp slt i64 %x, -16707583
467463
ret i1 %cmp
@@ -510,10 +506,8 @@ define i1 @almost_immediate_neg_uge_64(i64 %x) {
510506
define i1 @almost_immediate_neg_ult(i32 %x) {
511507
; CHECK-LABEL: almost_immediate_neg_ult:
512508
; CHECK: // %bb.0:
513-
; CHECK-NEXT: mov w8, #4097 // =0x1001
514-
; CHECK-NEXT: movk w8, #65281, lsl #16
515-
; CHECK-NEXT: cmp w0, w8
516-
; CHECK-NEXT: cset w0, lo
509+
; CHECK-NEXT: cmn w0, #4079, lsl #12 // =16707584
510+
; CHECK-NEXT: cset w0, ls
517511
; CHECK-NEXT: ret
518512
%cmp = icmp ult i32 %x, -16707583
519513
ret i1 %cmp
@@ -522,10 +516,8 @@ define i1 @almost_immediate_neg_ult(i32 %x) {
522516
define i1 @almost_immediate_neg_ult_64(i64 %x) {
523517
; CHECK-LABEL: almost_immediate_neg_ult_64:
524518
; CHECK: // %bb.0:
525-
; CHECK-NEXT: mov x8, #-61439 // =0xffffffffffff1001
526-
; CHECK-NEXT: movk x8, #65281, lsl #16
527-
; CHECK-NEXT: cmp x0, x8
528-
; CHECK-NEXT: cset w0, lo
519+
; CHECK-NEXT: cmn x0, #4079, lsl #12 // =16707584
520+
; CHECK-NEXT: cset w0, ls
529521
; CHECK-NEXT: ret
530522
%cmp = icmp ult i64 %x, -16707583
531523
ret i1 %cmp
@@ -554,9 +546,8 @@ define i1 @almost_immediate_neg_sle_64(i64 %x) {
554546
define i1 @almost_immediate_neg_sgt(i32 %x) {
555547
; CHECK-LABEL: almost_immediate_neg_sgt:
556548
; CHECK: // %bb.0:
557-
; CHECK-NEXT: mov w8, #-16773121 // =0xff000fff
558-
; CHECK-NEXT: cmp w0, w8
559-
; CHECK-NEXT: cset w0, gt
549+
; CHECK-NEXT: cmn w0, #4095, lsl #12 // =16773120
550+
; CHECK-NEXT: cset w0, ge
560551
; CHECK-NEXT: ret
561552
%cmp = icmp sgt i32 %x, -16773121
562553
ret i1 %cmp
@@ -565,9 +556,8 @@ define i1 @almost_immediate_neg_sgt(i32 %x) {
565556
define i1 @almost_immediate_neg_sgt_64(i64 %x) {
566557
; CHECK-LABEL: almost_immediate_neg_sgt_64:
567558
; CHECK: // %bb.0:
568-
; CHECK-NEXT: mov x8, #-16773121 // =0xffffffffff000fff
569-
; CHECK-NEXT: cmp x0, x8
570-
; CHECK-NEXT: cset w0, gt
559+
; CHECK-NEXT: cmn x0, #4095, lsl #12 // =16773120
560+
; CHECK-NEXT: cset w0, ge
571561
; CHECK-NEXT: ret
572562
%cmp = icmp sgt i64 %x, -16773121
573563
ret i1 %cmp
@@ -596,9 +586,8 @@ define i1 @almost_immediate_neg_ule_64(i64 %x) {
596586
define i1 @almost_immediate_neg_ugt(i32 %x) {
597587
; CHECK-LABEL: almost_immediate_neg_ugt:
598588
; CHECK: // %bb.0:
599-
; CHECK-NEXT: mov w8, #-16773121 // =0xff000fff
600-
; CHECK-NEXT: cmp w0, w8
601-
; CHECK-NEXT: cset w0, hi
589+
; CHECK-NEXT: cmn w0, #4095, lsl #12 // =16773120
590+
; CHECK-NEXT: cset w0, hs
602591
; CHECK-NEXT: ret
603592
%cmp = icmp ugt i32 %x, -16773121
604593
ret i1 %cmp
@@ -607,9 +596,8 @@ define i1 @almost_immediate_neg_ugt(i32 %x) {
607596
define i1 @almost_immediate_neg_ugt_64(i64 %x) {
608597
; CHECK-LABEL: almost_immediate_neg_ugt_64:
609598
; CHECK: // %bb.0:
610-
; CHECK-NEXT: mov x8, #-16773121 // =0xffffffffff000fff
611-
; CHECK-NEXT: cmp x0, x8
612-
; CHECK-NEXT: cset w0, hi
599+
; CHECK-NEXT: cmn x0, #4095, lsl #12 // =16773120
600+
; CHECK-NEXT: cset w0, hs
613601
; CHECK-NEXT: ret
614602
%cmp = icmp ugt i64 %x, -16773121
615603
ret i1 %cmp

‎llvm/test/CodeGen/AArch64/csel-subs-swapped.ll

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -44,10 +44,8 @@ define i32 @sge_i32(i32 %x) {
4444
; CHECK-LABEL: sge_i32:
4545
; CHECK: // %bb.0:
4646
; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
47-
; CHECK-NEXT: mov w9, #-2097153 // =0xffdfffff
48-
; CHECK-NEXT: sub w8, w8, w0
49-
; CHECK-NEXT: cmp w0, w9
50-
; CHECK-NEXT: csel w0, w0, w8, gt
47+
; CHECK-NEXT: subs w8, w8, w0
48+
; CHECK-NEXT: csel w0, w0, w8, le
5149
; CHECK-NEXT: ret
5250
%cmp = icmp sge i32 %x, -2097152
5351
%sub = sub i32 -2097152, %x
@@ -72,10 +70,8 @@ define i32 @sle_i32(i32 %x) {
7270
; CHECK-LABEL: sle_i32:
7371
; CHECK: // %bb.0:
7472
; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
75-
; CHECK-NEXT: mov w9, #-2097151 // =0xffe00001
76-
; CHECK-NEXT: sub w8, w8, w0
77-
; CHECK-NEXT: cmp w0, w9
78-
; CHECK-NEXT: csel w0, w0, w8, lt
73+
; CHECK-NEXT: subs w8, w8, w0
74+
; CHECK-NEXT: csel w0, w0, w8, ge
7975
; CHECK-NEXT: ret
8076
%cmp = icmp sle i32 %x, -2097152
8177
%sub = sub i32 -2097152, %x
@@ -128,10 +124,8 @@ define i32 @ule_i32(i32 %x) {
128124
; CHECK-LABEL: ule_i32:
129125
; CHECK: // %bb.0:
130126
; CHECK-NEXT: mov w8, #-2097152 // =0xffe00000
131-
; CHECK-NEXT: mov w9, #-2097151 // =0xffe00001
132-
; CHECK-NEXT: sub w8, w8, w0
133-
; CHECK-NEXT: cmp w0, w9
134-
; CHECK-NEXT: csel w0, w0, w8, lo
127+
; CHECK-NEXT: subs w8, w8, w0
128+
; CHECK-NEXT: csel w0, w0, w8, hs
135129
; CHECK-NEXT: ret
136130
%cmp = icmp ule i32 %x, -2097152
137131
%sub = sub i32 -2097152, %x

‎llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,9 @@ define i1 @test_signed_i1_f32(float %f) nounwind {
2323
; CHECK-SD-LABEL: test_signed_i1_f32:
2424
; CHECK-SD: // %bb.0:
2525
; CHECK-SD-NEXT: fcvtzs w8, s0
26-
; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
27-
; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
26+
; CHECK-SD-NEXT: and w8, w8, w8, asr #31
27+
; CHECK-SD-NEXT: cmn w8, #1
28+
; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
2829
; CHECK-SD-NEXT: and w0, w8, #0x1
2930
; CHECK-SD-NEXT: ret
3031
;
@@ -268,8 +269,9 @@ define i1 @test_signed_i1_f64(double %f) nounwind {
268269
; CHECK-SD-LABEL: test_signed_i1_f64:
269270
; CHECK-SD: // %bb.0:
270271
; CHECK-SD-NEXT: fcvtzs w8, d0
271-
; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
272-
; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
272+
; CHECK-SD-NEXT: and w8, w8, w8, asr #31
273+
; CHECK-SD-NEXT: cmn w8, #1
274+
; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
273275
; CHECK-SD-NEXT: and w0, w8, #0x1
274276
; CHECK-SD-NEXT: ret
275277
;
@@ -518,16 +520,18 @@ define i1 @test_signed_i1_f16(half %f) nounwind {
518520
; CHECK-SD-CVT: // %bb.0:
519521
; CHECK-SD-CVT-NEXT: fcvt s0, h0
520522
; CHECK-SD-CVT-NEXT: fcvtzs w8, s0
521-
; CHECK-SD-CVT-NEXT: ands w8, w8, w8, asr #31
522-
; CHECK-SD-CVT-NEXT: csinv w8, w8, wzr, ge
523+
; CHECK-SD-CVT-NEXT: and w8, w8, w8, asr #31
524+
; CHECK-SD-CVT-NEXT: cmn w8, #1
525+
; CHECK-SD-CVT-NEXT: csinv w8, w8, wzr, gt
523526
; CHECK-SD-CVT-NEXT: and w0, w8, #0x1
524527
; CHECK-SD-CVT-NEXT: ret
525528
;
526529
; CHECK-SD-FP16-LABEL: test_signed_i1_f16:
527530
; CHECK-SD-FP16: // %bb.0:
528531
; CHECK-SD-FP16-NEXT: fcvtzs w8, h0
529-
; CHECK-SD-FP16-NEXT: ands w8, w8, w8, asr #31
530-
; CHECK-SD-FP16-NEXT: csinv w8, w8, wzr, ge
532+
; CHECK-SD-FP16-NEXT: and w8, w8, w8, asr #31
533+
; CHECK-SD-FP16-NEXT: cmn w8, #1
534+
; CHECK-SD-FP16-NEXT: csinv w8, w8, wzr, gt
531535
; CHECK-SD-FP16-NEXT: and w0, w8, #0x1
532536
; CHECK-SD-FP16-NEXT: ret
533537
;

‎llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2371,10 +2371,12 @@ define <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
23712371
; CHECK-SD-NEXT: mov d1, v0.d[1]
23722372
; CHECK-SD-NEXT: fcvtzs w9, d0
23732373
; CHECK-SD-NEXT: fcvtzs w8, d1
2374-
; CHECK-SD-NEXT: ands w8, w8, w8, asr #31
2375-
; CHECK-SD-NEXT: csinv w8, w8, wzr, ge
2376-
; CHECK-SD-NEXT: ands w9, w9, w9, asr #31
2377-
; CHECK-SD-NEXT: csinv w9, w9, wzr, ge
2374+
; CHECK-SD-NEXT: and w9, w9, w9, asr #31
2375+
; CHECK-SD-NEXT: and w8, w8, w8, asr #31
2376+
; CHECK-SD-NEXT: cmn w8, #1
2377+
; CHECK-SD-NEXT: csinv w8, w8, wzr, gt
2378+
; CHECK-SD-NEXT: cmn w9, #1
2379+
; CHECK-SD-NEXT: csinv w9, w9, wzr, gt
23782380
; CHECK-SD-NEXT: fmov s0, w9
23792381
; CHECK-SD-NEXT: mov v0.s[1], w8
23802382
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0

‎llvm/test/CodeGen/AArch64/select-constant-xor.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -168,8 +168,8 @@ define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
168168
define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
169169
; CHECK-SD-LABEL: icmpasrne:
170170
; CHECK-SD: // %bb.0:
171-
; CHECK-SD-NEXT: cmp w0, #0
172-
; CHECK-SD-NEXT: csel w0, w1, w2, ge
171+
; CHECK-SD-NEXT: cmn w0, #1
172+
; CHECK-SD-NEXT: csel w0, w1, w2, gt
173173
; CHECK-SD-NEXT: ret
174174
;
175175
; CHECK-GI-LABEL: icmpasrne:

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