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[RISCV] Refine location size for segment spill and fill (#133268)
This is a follow up to #133171. I realized we could assume the structure of the previous MMO, and thus the split is much simpler than I'd initially pictured.
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6 files changed

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-166
lines changed

6 files changed

+170
-166
lines changed

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -408,8 +408,10 @@ void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const {
408408
Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
409409

410410
auto *OldMMO = *(II->memoperands_begin());
411-
auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(),
412-
LocationSize::beforeOrAfterPointer());
411+
LocationSize OldLoc = OldMMO->getSize();
412+
assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
413+
TypeSize NewSize = OldLoc.getValue().divideCoefficientBy(NF);
414+
auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(), NewSize);
413415
for (unsigned I = 0; I < NF; ++I) {
414416
// Adding implicit-use of super register to describe we are using part of
415417
// super register, that prevents machine verifier complaining when part of
@@ -488,8 +490,10 @@ void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const {
488490
bool IsBaseKill = II->getOperand(1).isKill();
489491
Register NewBase = MRI.createVirtualRegister(&RISCV::GPRRegClass);
490492
auto *OldMMO = *(II->memoperands_begin());
491-
auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(),
492-
LocationSize::beforeOrAfterPointer());
493+
LocationSize OldLoc = OldMMO->getSize();
494+
assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
495+
TypeSize NewSize = OldLoc.getValue().divideCoefficientBy(NF);
496+
auto *NewMMO = MF.getMachineMemOperand(OldMMO, OldMMO->getOffset(), NewSize);
493497
for (unsigned I = 0; I < NF; ++I) {
494498
BuildMI(MBB, II, DL, TII->get(Opcode),
495499
TRI->getSubReg(DestReg, SubRegIdx + I))

‎llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -42,13 +42,13 @@ define void @_Z3foov() {
4242
; CHECK-NEXT: addi a0, sp, 16
4343
; CHECK-NEXT: csrr a1, vlenb
4444
; CHECK-NEXT: slli a1, a1, 1
45-
; CHECK-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
45+
; CHECK-NEXT: vs2r.v v8, (a0) # vscale x 16-byte Folded Spill
4646
; CHECK-NEXT: add a0, a0, a1
47-
; CHECK-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
47+
; CHECK-NEXT: vs2r.v v10, (a0) # vscale x 16-byte Folded Spill
4848
; CHECK-NEXT: add a0, a0, a1
49-
; CHECK-NEXT: vs2r.v v12, (a0) # Unknown-size Folded Spill
49+
; CHECK-NEXT: vs2r.v v12, (a0) # vscale x 16-byte Folded Spill
5050
; CHECK-NEXT: add a0, a0, a1
51-
; CHECK-NEXT: vs2r.v v14, (a0) # Unknown-size Folded Spill
51+
; CHECK-NEXT: vs2r.v v14, (a0) # vscale x 16-byte Folded Spill
5252
; CHECK-NEXT: lui a0, %hi(.L__const._Z3foov.var_40)
5353
; CHECK-NEXT: addi a0, a0, %lo(.L__const._Z3foov.var_40)
5454
; CHECK-NEXT: #APP
@@ -61,13 +61,13 @@ define void @_Z3foov() {
6161
; CHECK-NEXT: addi a0, sp, 16
6262
; CHECK-NEXT: csrr a1, vlenb
6363
; CHECK-NEXT: slli a1, a1, 1
64-
; CHECK-NEXT: vl2r.v v8, (a0) # Unknown-size Folded Reload
64+
; CHECK-NEXT: vl2r.v v8, (a0) # vscale x 16-byte Folded Reload
6565
; CHECK-NEXT: add a0, a0, a1
66-
; CHECK-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
66+
; CHECK-NEXT: vl2r.v v10, (a0) # vscale x 16-byte Folded Reload
6767
; CHECK-NEXT: add a0, a0, a1
68-
; CHECK-NEXT: vl2r.v v12, (a0) # Unknown-size Folded Reload
68+
; CHECK-NEXT: vl2r.v v12, (a0) # vscale x 16-byte Folded Reload
6969
; CHECK-NEXT: add a0, a0, a1
70-
; CHECK-NEXT: vl2r.v v14, (a0) # Unknown-size Folded Reload
70+
; CHECK-NEXT: vl2r.v v14, (a0) # vscale x 16-byte Folded Reload
7171
; CHECK-NEXT: csrr a0, vlenb
7272
; CHECK-NEXT: slli a0, a0, 3
7373
; CHECK-NEXT: add a0, sp, a0

‎llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -34,9 +34,9 @@ define void @last_chance_recoloring_failure() {
3434
; CHECK-NEXT: addi a0, a0, 16
3535
; CHECK-NEXT: csrr a1, vlenb
3636
; CHECK-NEXT: slli a1, a1, 2
37-
; CHECK-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill
37+
; CHECK-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
3838
; CHECK-NEXT: add a0, a0, a1
39-
; CHECK-NEXT: vs4r.v v20, (a0) # Unknown-size Folded Spill
39+
; CHECK-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
4040
; CHECK-NEXT: li s0, 36
4141
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
4242
; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t
@@ -49,9 +49,9 @@ define void @last_chance_recoloring_failure() {
4949
; CHECK-NEXT: addi a0, a0, 16
5050
; CHECK-NEXT: csrr a1, vlenb
5151
; CHECK-NEXT: slli a1, a1, 2
52-
; CHECK-NEXT: vl4r.v v16, (a0) # Unknown-size Folded Reload
52+
; CHECK-NEXT: vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
5353
; CHECK-NEXT: add a0, a0, a1
54-
; CHECK-NEXT: vl4r.v v20, (a0) # Unknown-size Folded Reload
54+
; CHECK-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
5555
; CHECK-NEXT: addi a0, sp, 16
5656
; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
5757
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
@@ -94,9 +94,9 @@ define void @last_chance_recoloring_failure() {
9494
; SUBREGLIVENESS-NEXT: addi a0, a0, 16
9595
; SUBREGLIVENESS-NEXT: csrr a1, vlenb
9696
; SUBREGLIVENESS-NEXT: slli a1, a1, 2
97-
; SUBREGLIVENESS-NEXT: vs4r.v v16, (a0) # Unknown-size Folded Spill
97+
; SUBREGLIVENESS-NEXT: vs4r.v v16, (a0) # vscale x 32-byte Folded Spill
9898
; SUBREGLIVENESS-NEXT: add a0, a0, a1
99-
; SUBREGLIVENESS-NEXT: vs4r.v v20, (a0) # Unknown-size Folded Spill
99+
; SUBREGLIVENESS-NEXT: vs4r.v v20, (a0) # vscale x 32-byte Folded Spill
100100
; SUBREGLIVENESS-NEXT: li s0, 36
101101
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
102102
; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t
@@ -109,9 +109,9 @@ define void @last_chance_recoloring_failure() {
109109
; SUBREGLIVENESS-NEXT: addi a0, a0, 16
110110
; SUBREGLIVENESS-NEXT: csrr a1, vlenb
111111
; SUBREGLIVENESS-NEXT: slli a1, a1, 2
112-
; SUBREGLIVENESS-NEXT: vl4r.v v16, (a0) # Unknown-size Folded Reload
112+
; SUBREGLIVENESS-NEXT: vl4r.v v16, (a0) # vscale x 32-byte Folded Reload
113113
; SUBREGLIVENESS-NEXT: add a0, a0, a1
114-
; SUBREGLIVENESS-NEXT: vl4r.v v20, (a0) # Unknown-size Folded Reload
114+
; SUBREGLIVENESS-NEXT: vl4r.v v20, (a0) # vscale x 32-byte Folded Reload
115115
; SUBREGLIVENESS-NEXT: addi a0, sp, 16
116116
; SUBREGLIVENESS-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
117117
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma

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