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Change-Id: I5d1cada783bb3da0a5d51fd10c98428d63db9c13
1 parent 7b13365 commit b67e3f7

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6 files changed

+49
-40
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6 files changed

+49
-40
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3155,9 +3155,9 @@ class TargetLoweringBase {
31553155
///
31563156
/// \p DI is the deinterleave intrinsic.
31573157
/// \p LI is the accompanying load instruction
3158-
virtual bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI,
3159-
LoadInst *LI,
3160-
SmallVectorImpl<Instruction *> &DeadInsts) const {
3158+
virtual bool lowerDeinterleaveIntrinsicToLoad(
3159+
IntrinsicInst *DI, LoadInst *LI,
3160+
SmallVectorImpl<Instruction *> &DeadInsts) const {
31613161
return false;
31623162
}
31633163

@@ -3167,9 +3167,9 @@ class TargetLoweringBase {
31673167
///
31683168
/// \p II is the interleave intrinsic.
31693169
/// \p SI is the accompanying store instruction
3170-
virtual bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
3171-
StoreInst *SI,
3172-
SmallVectorImpl<Instruction *> &DeadInstructions) const {
3170+
virtual bool lowerInterleaveIntrinsicToStore(
3171+
IntrinsicInst *II, StoreInst *SI,
3172+
SmallVectorImpl<Instruction *> &DeadInstructions) const {
31733173
return false;
31743174
}
31753175

‎llvm/lib/CodeGen/InterleavedAccessPass.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -518,7 +518,8 @@ bool InterleavedAccessImpl::lowerInterleaveIntrinsic(
518518
// We now have a target-specific store, so delete the old one.
519519
DeadInsts.push_back(SI);
520520
DeadInsts.push_back(II);
521-
DeadInsts.insert(DeadInsts.end(), InterleaveDeadInsts.begin(), InterleaveDeadInsts.end());
521+
DeadInsts.insert(DeadInsts.end(), InterleaveDeadInsts.begin(),
522+
InterleaveDeadInsts.end());
522523
return true;
523524
}
524525

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 23 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -16906,9 +16906,9 @@ bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
1690616906
return true;
1690716907
}
1690816908

16909-
bool getDeinterleave2Values(
16910-
Value *DI, SmallVectorImpl<Instruction *> &DeinterleavedValues,
16911-
SmallVectorImpl<Instruction *> &DeadInsts) {
16909+
bool getDeinterleave2Values(Value *DI,
16910+
SmallVectorImpl<Instruction *> &DeinterleavedValues,
16911+
SmallVectorImpl<Instruction *> &DeadInsts) {
1691216912
if (!DI->hasNUses(2))
1691316913
return false;
1691416914
auto *Extr1 = dyn_cast<ExtractValueInst>(*(DI->user_begin()));
@@ -16930,7 +16930,8 @@ bool getDeinterleave2Values(
1693016930
return false;
1693116931
}
1693216932
// DeinterleavedValues will be replace by output of ld2
16933-
DeadInsts.insert(DeadInsts.end(), DeinterleavedValues.begin(), DeinterleavedValues.end());
16933+
DeadInsts.insert(DeadInsts.end(), DeinterleavedValues.begin(),
16934+
DeinterleavedValues.end());
1693416935
return true;
1693516936
}
1693616937

@@ -16946,9 +16947,10 @@ DeinterleaveIntrinsic tree:
1694616947
| | | |
1694716948
roots: A C B D
1694816949
roots in correct order of DI4 will be: A B C D.
16949-
Returns true if `DI` is the top of an IR tree that represents a theoretical vector.deinterleave4 intrinsic.
16950-
When true is returned, `DeinterleavedValues` vector is populated with the results such an intrinsic would return:
16951-
(i.e. {A, B, C, D } = vector.deinterleave4(...))
16950+
Returns true if `DI` is the top of an IR tree that represents a theoretical
16951+
vector.deinterleave4 intrinsic. When true is returned, `DeinterleavedValues`
16952+
vector is populated with the results such an intrinsic would return: (i.e. {A,
16953+
B, C, D } = vector.deinterleave4(...))
1695216954
*/
1695316955
bool getDeinterleave4Values(Value *DI,
1695416956
SmallVectorImpl<Instruction *> &DeinterleavedValues,
@@ -16972,7 +16974,8 @@ bool getDeinterleave4Values(Value *DI,
1697216974
auto *C = dyn_cast<ExtractValueInst>(*(++DI1->user_begin()));
1697316975
auto *B = dyn_cast<ExtractValueInst>(*(DI2->user_begin()));
1697416976
auto *D = dyn_cast<ExtractValueInst>(*(++DI2->user_begin()));
16975-
// Make sure that the A,B,C and D are ExtractValue instructions before getting the extract index
16977+
// Make sure that the A,B,C and D are ExtractValue instructions before getting
16978+
// the extract index
1697616979
if (!A || !B || !C || !D)
1697716980
return false;
1697816981

@@ -17005,7 +17008,8 @@ bool getDeinterleave4Values(Value *DI,
1700517008

1700617009
// These Values will not be used anymore,
1700717010
// DI4 will be created instead of nested DI1 and DI2
17008-
DeadInsts.insert(DeadInsts.end(), DeinterleavedValues.begin(), DeinterleavedValues.end());
17011+
DeadInsts.insert(DeadInsts.end(), DeinterleavedValues.begin(),
17012+
DeinterleavedValues.end());
1700917013
DeadInsts.push_back(cast<Instruction>(DI1));
1701017014
DeadInsts.push_back(cast<Instruction>(Extr1));
1701117015
DeadInsts.push_back(cast<Instruction>(DI2));
@@ -17023,7 +17027,8 @@ bool getDeinterleavedValues(Value *DI,
1702317027
}
1702417028

1702517029
bool AArch64TargetLowering::lowerDeinterleaveIntrinsicToLoad(
17026-
IntrinsicInst *DI, LoadInst *LI, SmallVectorImpl<Instruction *> &DeadInsts) const {
17030+
IntrinsicInst *DI, LoadInst *LI,
17031+
SmallVectorImpl<Instruction *> &DeadInsts) const {
1702717032
// Only deinterleave2 supported at present.
1702817033
if (DI->getIntrinsicID() != Intrinsic::vector_deinterleave2)
1702917034
return false;
@@ -17116,9 +17121,10 @@ InterleaveIntrinsic tree.
1711617121
[II]
1711717122

1711817123
values in correct order of interleave4: A B C D.
17119-
Returns true if `II` is the root of an IR tree that represents a theoretical vector.interleave4 intrinsic.
17120-
When true is returned, `ValuesToInterleave` vector is populated with the inputs such an intrinsic would take:
17121-
(i.e. vector.interleave4(A, B, C, D)).
17124+
Returns true if `II` is the root of an IR tree that represents a theoretical
17125+
vector.interleave4 intrinsic. When true is returned, `ValuesToInterleave` vector
17126+
is populated with the inputs such an intrinsic would take: (i.e.
17127+
vector.interleave4(A, B, C, D)).
1712217128
*/
1712317129
bool getValuesToInterleave(Value *II,
1712417130
SmallVectorImpl<Value *> &ValuesToInterleave,
@@ -17133,7 +17139,8 @@ bool getValuesToInterleave(Value *II,
1713317139
ValuesToInterleave.push_back(D);
1713417140
// intermediate II will not be needed anymore
1713517141
Value *II1, *II2;
17136-
assert(match(II, m_Interleave2(m_Value(II1), m_Value(II2))) && "II tree is expected");
17142+
assert(match(II, m_Interleave2(m_Value(II1), m_Value(II2))) &&
17143+
"II tree is expected");
1713717144
DeadInsts.push_back(cast<Instruction>(II1));
1713817145
DeadInsts.push_back(cast<Instruction>(II2));
1713917146
return true;
@@ -17150,7 +17157,8 @@ bool getValuesToInterleave(Value *II,
1715017157
}
1715117158

1715217159
bool AArch64TargetLowering::lowerInterleaveIntrinsicToStore(
17153-
IntrinsicInst *II, StoreInst *SI, SmallVectorImpl<Instruction *> &DeadInsts) const {
17160+
IntrinsicInst *II, StoreInst *SI,
17161+
SmallVectorImpl<Instruction *> &DeadInsts) const {
1715417162
// Only interleave2 supported at present.
1715517163
if (II->getIntrinsicID() != Intrinsic::vector_interleave2)
1715617164
return false;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -703,13 +703,13 @@ class AArch64TargetLowering : public TargetLowering {
703703
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
704704
unsigned Factor) const override;
705705

706-
bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI,
707-
LoadInst *LI,
708-
SmallVectorImpl<Instruction *> &DeadInsts) const override;
706+
bool lowerDeinterleaveIntrinsicToLoad(
707+
IntrinsicInst *DI, LoadInst *LI,
708+
SmallVectorImpl<Instruction *> &DeadInsts) const override;
709709

710-
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
711-
StoreInst *SI,
712-
SmallVectorImpl<Instruction *> &DeadInsts) const override;
710+
bool lowerInterleaveIntrinsicToStore(
711+
IntrinsicInst *II, StoreInst *SI,
712+
SmallVectorImpl<Instruction *> &DeadInsts) const override;
713713

714714
bool isLegalAddImmediate(int64_t) const override;
715715
bool isLegalAddScalableImmediate(int64_t) const override;

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -21775,9 +21775,9 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
2177521775
return true;
2177621776
}
2177721777

21778-
bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI,
21779-
LoadInst *LI,
21780-
SmallVectorImpl<Instruction *> &DeadInsts) const {
21778+
bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(
21779+
IntrinsicInst *DI, LoadInst *LI,
21780+
SmallVectorImpl<Instruction *> &DeadInsts) const {
2178121781
assert(LI->isSimple());
2178221782
IRBuilder<> Builder(LI);
2178321783

@@ -21826,9 +21826,9 @@ bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI,
2182621826
return true;
2182721827
}
2182821828

21829-
bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
21830-
StoreInst *SI,
21831-
SmallVectorImpl<Instruction *> &DeadInstructions) const {
21829+
bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(
21830+
IntrinsicInst *II, StoreInst *SI,
21831+
SmallVectorImpl<Instruction *> &DeadInstructions) const {
2183221832
assert(SI->isSimple());
2183321833
IRBuilder<> Builder(SI);
2183421834

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -876,13 +876,13 @@ class RISCVTargetLowering : public TargetLowering {
876876
bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
877877
unsigned Factor) const override;
878878

879-
bool lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *II,
880-
LoadInst *LI,
881-
SmallVectorImpl<Instruction *> &DeadInsts) const override;
879+
bool lowerDeinterleaveIntrinsicToLoad(
880+
IntrinsicInst *II, LoadInst *LI,
881+
SmallVectorImpl<Instruction *> &DeadInsts) const override;
882882

883-
bool lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
884-
StoreInst *SI,
885-
SmallVectorImpl<Instruction *> &DeadInsts) const override;
883+
bool lowerInterleaveIntrinsicToStore(
884+
IntrinsicInst *II, StoreInst *SI,
885+
SmallVectorImpl<Instruction *> &DeadInsts) const override;
886886

887887
bool supportKCFIBundles() const override { return true; }
888888

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