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[RISCV] Make M imply Zmmul
According to the spec, M implies Zmmul.
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9 files changed

+41
-44
lines changed

9 files changed

+41
-44
lines changed

‎clang/lib/Basic/Targets/RISCV.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
168168
Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor)));
169169
}
170170

171-
if (ISAInfo->hasExtension("m") || ISAInfo->hasExtension("zmmul"))
171+
if (ISAInfo->hasExtension("zmmul"))
172172
Builder.defineMacro("__riscv_mul");
173173

174174
if (ISAInfo->hasExtension("m")) {

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -305,7 +305,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
305305
getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE, G_CONSTANT_POOL})
306306
.legalFor({p0});
307307

308-
if (ST.hasStdExtM() || ST.hasStdExtZmmul()) {
308+
if (ST.hasStdExtZmmul()) {
309309
getActionDefinitionsBuilder(G_MUL)
310310
.legalFor({s32, sXLen})
311311
.widenScalarToNextPow2(0)

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -171,23 +171,21 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
171171

172172
// Multiply Extensions
173173

174+
def FeatureStdExtZmmul
175+
: RISCVExtension<"zmmul", 1, 0,
176+
"'Zmmul' (Integer Multiplication)">;
177+
def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
178+
AssemblerPredicate<(all_of FeatureStdExtZmmul),
179+
"'Zmmul' (Integer Multiplication)">;
180+
174181
def FeatureStdExtM
175182
: RISCVExtension<"m", 2, 0,
176-
"'M' (Integer Multiplication and Division)">;
183+
"'M' (Integer Multiplication and Division)",
184+
[FeatureStdExtZmmul]>;
177185
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
178186
AssemblerPredicate<(all_of FeatureStdExtM),
179187
"'M' (Integer Multiplication and Division)">;
180188

181-
def FeatureStdExtZmmul
182-
: RISCVExtension<"zmmul", 1, 0,
183-
"'Zmmul' (Integer Multiplication)">;
184-
185-
def HasStdExtMOrZmmul
186-
: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
187-
AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
188-
"'M' (Integer Multiplication and Division) or "
189-
"'Zmmul' (Integer Multiplication)">;
190-
191189
// Atomic Extensions
192190

193191
def FeatureStdExtA

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -300,7 +300,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
300300
setLibcallName(RTLIB::MULO_I64, nullptr);
301301
}
302302

303-
if (!Subtarget.hasStdExtM() && !Subtarget.hasStdExtZmmul()) {
303+
if (!Subtarget.hasStdExtZmmul()) {
304304
setOperationAction({ISD::MUL, ISD::MULHS, ISD::MULHU}, XLenVT, Expand);
305305
if (RV64LegalI32 && Subtarget.is64Bit())
306306
setOperationAction(ISD::MUL, MVT::i32, Promote);
@@ -21012,14 +21012,13 @@ bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned)
2101221012
bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
2101321013
SDValue C) const {
2101421014
// Check integral scalar types.
21015-
const bool HasExtMOrZmmul =
21016-
Subtarget.hasStdExtM() || Subtarget.hasStdExtZmmul();
21015+
const bool HasZmmul = Subtarget.hasStdExtZmmul();
2101721016
if (!VT.isScalarInteger())
2101821017
return false;
2101921018

2102021019
// Omit the optimization if the sub target has the M extension and the data
2102121020
// size exceeds XLen.
21022-
if (HasExtMOrZmmul && VT.getSizeInBits() > Subtarget.getXLen())
21021+
if (HasZmmul && VT.getSizeInBits() > Subtarget.getXLen())
2102321022
return false;
2102421023

2102521024
if (auto *ConstNode = dyn_cast<ConstantSDNode>(C.getNode())) {

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3695,7 +3695,7 @@ void RISCVInstrInfo::mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
36953695
.addReg(ScaledRegister, RegState::Kill)
36963696
.addReg(DestReg, RegState::Kill)
36973697
.setMIFlag(Flag);
3698-
} else if (STI.hasStdExtM() || STI.hasStdExtZmmul()) {
3698+
} else if (STI.hasStdExtZmmul()) {
36993699
Register N = MRI.createVirtualRegister(&RISCV::GPRRegClass);
37003700
movImm(MBB, II, DL, N, Amount, Flag);
37013701
BuildMI(MBB, II, DL, get(RISCV::MUL), DestReg)

‎llvm/lib/Target/RISCV/RISCVInstrInfoM.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ def riscv_remuw : SDNode<"RISCVISD::REMUW", SDT_RISCVIntBinOpW>;
2424
// Instructions
2525
//===----------------------------------------------------------------------===//
2626

27-
let Predicates = [HasStdExtMOrZmmul] in {
27+
let Predicates = [HasStdExtZmmul] in {
2828
def MUL : ALU_rr<0b0000001, 0b000, "mul", Commutable=1>,
2929
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
3030
def MULH : ALU_rr<0b0000001, 0b001, "mulh", Commutable=1>,
@@ -33,7 +33,7 @@ def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
3333
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
3434
def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", Commutable=1>,
3535
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
36-
} // Predicates = [HasStdExtMOrZmmul]
36+
} // Predicates = [HasStdExtZmmul]
3737

3838
let Predicates = [HasStdExtM] in {
3939
def DIV : ALU_rr<0b0000001, 0b100, "div">,
@@ -46,10 +46,10 @@ def REMU : ALU_rr<0b0000001, 0b111, "remu">,
4646
Sched<[WriteIRem, ReadIRem, ReadIRem]>;
4747
} // Predicates = [HasStdExtM]
4848

49-
let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in {
49+
let Predicates = [HasStdExtZmmul, IsRV64], IsSignExtendingOpW = 1 in {
5050
def MULW : ALUW_rr<0b0000001, 0b000, "mulw", Commutable=1>,
5151
Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
52-
} // Predicates = [HasStdExtMOrZmmul, IsRV64]
52+
} // Predicates = [HasStdExtZmmul, IsRV64]
5353

5454
let Predicates = [HasStdExtM, IsRV64], IsSignExtendingOpW = 1 in {
5555
def DIVW : ALUW_rr<0b0000001, 0b100, "divw">,
@@ -66,12 +66,12 @@ def REMUW : ALUW_rr<0b0000001, 0b111, "remuw">,
6666
// Pseudo-instructions and codegen patterns
6767
//===----------------------------------------------------------------------===//
6868

69-
let Predicates = [HasStdExtMOrZmmul] in {
69+
let Predicates = [HasStdExtZmmul] in {
7070
def : PatGprGpr<mul, MUL>;
7171
def : PatGprGpr<mulhs, MULH>;
7272
def : PatGprGpr<mulhu, MULHU>;
7373
def : PatGprGpr<riscv_mulhsu, MULHSU>;
74-
} // Predicates = [HasStdExtMOrZmmul]
74+
} // Predicates = [HasStdExtZmmul]
7575

7676
let Predicates = [HasStdExtM] in {
7777
def : PatGprGpr<sdiv, DIV>;
@@ -81,7 +81,7 @@ def : PatGprGpr<urem, REMU>;
8181
} // Predicates = [HasStdExtM]
8282

8383
// Select W instructions if only the lower 32-bits of the result are used.
84-
let Predicates = [HasStdExtMOrZmmul, IsRV64] in
84+
let Predicates = [HasStdExtZmmul, IsRV64] in
8585
def : PatGprGpr<binop_allwusers<mul>, MULW>;
8686

8787
let Predicates = [HasStdExtM, IsRV64] in {
@@ -106,20 +106,20 @@ def : Pat<(srem (sexti32 (i64 GPR:$rs1)), (sexti32 (i64 GPR:$rs2))),
106106
(REMW GPR:$rs1, GPR:$rs2)>;
107107
} // Predicates = [HasStdExtM, IsRV64]
108108

109-
let Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba] in {
109+
let Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba] in {
110110
// Special case for calculating the full 64-bit product of a 32x32 unsigned
111111
// multiply where the inputs aren't known to be zero extended. We can shift the
112112
// inputs left by 32 and use a MULHU. This saves two SRLIs needed to finish
113113
// zeroing the upper 32 bits.
114114
def : Pat<(i64 (mul (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff))),
115115
(MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
116-
} // Predicates = [HasStdExtMOrZmmul, IsRV64, NotHasStdExtZba]
116+
} // Predicates = [HasStdExtZmmul, IsRV64, NotHasStdExtZba]
117117

118118
//===----------------------------------------------------------------------===//
119119
// Experimental RV64 i32 legalization patterns.
120120
//===----------------------------------------------------------------------===//
121121

122-
let Predicates = [HasStdExtMOrZmmul, IsRV64] in {
122+
let Predicates = [HasStdExtZmmul, IsRV64] in {
123123
def : PatGprGpr<mul, MULW, i32, i32>;
124124
}
125125

‎llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,7 @@ let Predicates = [HasStdExtZcb] in
183183
def C_ZEXT_B : RVZcArith_r<0b11000 , "c.zext.b">,
184184
Sched<[WriteIALU, ReadIALU]>;
185185

186-
let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in
186+
let Predicates = [HasStdExtZcb, HasStdExtZmmul] in
187187
def C_MUL : CA_ALU<0b100111, 0b10, "c.mul", GPRC>,
188188
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
189189

@@ -270,13 +270,13 @@ def CM_JALT : RVInst16CJ<0b101, 0b10, (outs), (ins uimm8ge32:$index),
270270
} // DecoderNamespace = "RVZcmt", Predicates = [HasStdExtZcmt]...
271271

272272

273-
let Predicates = [HasStdExtZcb, HasStdExtMOrZmmul] in{
273+
let Predicates = [HasStdExtZcb, HasStdExtZmmul] in{
274274
def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
275275
(C_MUL GPRC:$rs1, GPRC:$rs2)>;
276276
let isCompressOnly = true in
277277
def : CompressPat<(MUL GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
278278
(C_MUL GPRC:$rs1, GPRC:$rs2)>;
279-
} // Predicates = [HasStdExtZcb, HasStdExtMOrZmmul]
279+
} // Predicates = [HasStdExtZcb, HasStdExtZmmul]
280280

281281
let Predicates = [HasStdExtZcb, HasStdExtZbb] in{
282282
def : CompressPat<(SEXT_B GPRC:$rs1, GPRC:$rs1),

‎llvm/test/CodeGen/RISCV/attributes-module-flag.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@
33

44
; Test generation of ELF attribute from module metadata
55

6-
; RV32: .attribute 5, "rv32i2p1_m2p0_zba1p0"
7-
; RV64: .attribute 5, "rv64i2p1_m2p0_zba1p0"
6+
; RV32: .attribute 5, "rv32i2p1_m2p0_zmmul1p0_zba1p0"
7+
; RV64: .attribute 5, "rv64i2p1_m2p0_zmmul1p0_zba1p0"
88

99
define i32 @addi(i32 %a) {
1010
%1 = add i32 %a, 1

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@
273273

274274
; CHECK: .attribute 4, 16
275275

276-
; RV32M: .attribute 5, "rv32i2p1_m2p0"
276+
; RV32M: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
277277
; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
278278
; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
279279
; RV32A: .attribute 5, "rv32i2p1_a2p1"
@@ -398,7 +398,7 @@
398398
; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8"
399399
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
400400

401-
; RV64M: .attribute 5, "rv64i2p1_m2p0"
401+
; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
402402
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
403403
; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
404404
; RV64A: .attribute 5, "rv64i2p1_a2p1"
@@ -531,15 +531,15 @@
531531

532532
; RVI20U32: .attribute 5, "rv32i2p1"
533533
; RVI20U64: .attribute 5, "rv64i2p1"
534-
; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_za128rs1p0"
535-
; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"
536-
; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
537-
; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
538-
; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
539-
; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
540-
; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
541-
; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
542-
; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
534+
; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zmmul1p0_za128rs1p0"
535+
; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zmmul1p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0"
536+
; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
537+
; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
538+
; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
539+
; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
540+
; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
541+
; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
542+
; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
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define i32 @addi(i32 %a) {
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%1 = add i32 %a, 1

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